verilog中数组的定义，如何在verilog中初始化参数数组？
How can one initialize parameter type array in verilog where each of members are 32 bit hexadecimal notation numbers?
I have tried the following but it gives me syntax error.
parameter [31:0] k[0:63] = {32'habc132, 32'hba324f, ...};
定义数组初始化I'm using latest version of iverilog for compiling.
解决⽅案
On EDA Plyground The following example works using modelsim 10.1, the file has a .sv extension, causing it to be interpreted as SystemVerilog:
module test;
parameter [31:0] k [0:1] = {32'habc132, 32'hba324f};
initial begin
$displayh(k[0]);
$displayh(k[1]);
end
endmodule
If setting to SystemVerilog does not work or is not available for your simulator I suggest including the syntax error in the question.

版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。