A0.3V10-bit1.17f SAR ADC With Merge and Split Switching in90nm CMOS
Jin-Yi Lin and Chih-Cheng Hsieh
Abstract—This paper presents a10-bit ultra-low voltage en-ergy-efficient SAR ADC.The proposed merge-and-split(MS) switching effectively reduces DAC switching energy by83%com-pared with conventional one without the need of extra reference voltage and the issue of common-mode voltage variation. To maintain good input linearity,a new double-bootstrapped sample-and-hold(S/H)circuit is proposed under an ultra-low voltage of0.3V.In addition,by employing asymmetric logic in SAR control,the leakage power is reduced with the penalty of slight conversion speed degradation.The test chip fabricated in 90nm CMOS occupied a core area of0.03.With a single 0.3V supply and a Nyquist rate input,the prototype consumes35 nW at90kS/s and achieves an ENOB of8.38bit and a SFDR of 78.2dB,respectively.The operation frequency is scalable up to2 MS/s and power supply range from0.3V to0.5V.The resultant FOMs are1.17-to-1.78fJ/conv.-step.
Index Terms—Low power,low voltage,SAR ADC.
I.I NTRODUCTION
I N THE PAST FEW years,with the advancement of large-
scale integrated circuits,there has been a growing interest in the design of wireless sensor network for implantable,portable, and wearable applications.These sensing devices are gener-ally used for detecting and monitoring biomedical or environ-mental signals such as electrocardiographic(ECG),electroen-cephalography(EEG),electromyography(EMG),temperature, humidity,sound,and so on.In the sensor nodes,the power should be supplied by energy harvesting technologies to reduce the maintenance cost for battery replacement.Most of the small size energy harvesting devices,such as solar cells,can generate extremely low output voltage,and limited power.Therefore,ul-tralow-voltage and low-power operation is inevitable for wire-less sensor nodes.
The sensed signals are usually digitized by ADCs with mod-erate resolution(8–12bits)and sampling rate(1–1000kS/s).In these applications,ADCs are the most critical and power hungry blocks.Among various ADC architectures,successive approx-imation register(SAR)ADC shows a better power efficiency. Furthermore,SAR ADC benefits from technology downscaling because of two major reasons:1)SAR ADC mainly consists of digital circuits which get faster in advanced technologies,and is compatible with digital processors;and2)SAR ADC is an
Manuscript received April28,2014;revised July14,2014and August04, 2014;accepted August06,2014.Date of current version January06,2015.This research is particularly supported by Na
tional Science Council,Taiwan under Contract NSC102-2221-E-007-132and102-2220-E-007-008.This paper was recommended by Associate Editor A.M.A.Ali.
The authors are with the Department of Electrical Engineering,National Tsing-Hua University,Hsinchu30013,Taiwan(e-mail:jinyilin19@gmail; hu.edu.tw).
Color versions of one or more of thefi
gures in this paper are available online at
Digital Object Identifier10.1109/TCSI.2014.2349571Fig.1.Common10-bit asynchronous SAR ADC.
opamp-free architecture.In other words,SAR ADC does not require high gain and high bandwidth opamps,which consume large static power,and suffer from short channel effect and low supply voltage in advanced process.These reasons arouse many researches on exploring SAR ADC in depth.
Power consumption in a SAR ADC mainly lies in the DAC network,the comparator,and the SAR control logics,and the leakage current needs to be carefully manipulated as well.Many researches have shown interests in reducing DAC switching power[1]–[5].Compared to the conventional switching se-quence,the energy-saving[1],charge average switching(CAS) [2],set-and-down[3],-based[4],and,partialfloating[5] switching sequences reduce switching energy by69%,74.8%, 81%,90%,and94%,respectively.To reduce comparator noise, data-driven noise reduction[6]and majority vote comparison [7]are proposed.With respect to digital circuit,reducing supply voltage and employing advanced technology is beneficial[1], [2],[6]–[14].However,analog circuits become challenging in low supply operation due to the reduced signal swing and barely turn-on resistance of MOS switch.In addition,by carefully selecting transistor size and threshold voltage,one could minimize the overall power consumption with the design trade-off between speed(dynamic power co
nsumption)and leakage current(static power consumption).
This brief aims at enhancing SAR ADC power effi-ciency by pushing down the supply voltage to0.3V and proposing low-voltage design techniques.For low voltage design,the simplest SAR architecture is preferred and em-ployed in this work,as shown in Fig.  1.Asynchronous clocking helps frequency scaling because only one external sampling clock is required.To overcome the non-linearity degraded by weakly turn-on switch,a new advanced double-boosted sample-and-hold(S/H)is proposed.In addition, a merge-and-split(MS)switching DAC without common-mode voltage shift is developed to reduce the switching energy of DAC network by83%compared to conventional one.Consid-ering leakage current,asymmetric logics and multi-threshold MOS devices are employed for the optimal SAR control logics with trade-off of speed and leakage power.
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Fig.2.Block diagram of the proposed10-bit asynchronous SAR ADC.
The paper is organized as follows.Section II introduces the MS switching method,and Section III describes the design and implementation of the SAR ADC.Measurement results are shown in Section IV and conclusions are given in Section V.
II.P ROPOSED ADC A RCHITECTURE
Fig.2shows the schematic of the proposed10-bit asyn-chronous SAR ADC.To suppress supply voltage noise and have good common-mode noise rejection,the fully differential architecture is employed.The DAC array is used as sampling capacitor and its MSB capacitor is split into sub-arrays.Thus, the DAC array is composed of two identical sub-DAC arrays called and,which are connected to and at sampling phase,respectively.By doing so, the DAC arrays can be switched on the opposite side,and maintain constant common-mode voltage at conversion phase. In addition,local boosted switches(,–9,11–19) are implemented for MS switching,and only two reference voltages of(VDD)and(gnd)are required.
Fig.3(a)CAS DAC switching[2]with a4-bit ex-ample.Since the implementation is symmetrical,only the
condition is illustrated for simplicity.During the sampling phase,the input signals are sampled onto the top plates of DAC,while and are reset to and and are reset to0.After the sampling phase,comparator
makesfirst decision directly without switching any capacitor,and the result is
(for).Then,the2C of and are switched to0and to generate a1/2shift on top plates.If,the necessary 1/4shift on top plates is accomplished by switching the1C of and to0and,respectively. Nevertheless,If, the required1/4shift on top plates is accomplished by merging the2C in and.The same procedure is conducted until the bit isfinished.
Fig.3(b)shows the proposed MS DAC switching with a4-bit example.During the sampling phase,the input signals are sam-pled onto the top plates of DAC,while and
are reset to and and are reset to0.Next, the comparator makesfidecision directly,and the result is (for).Then,all the capacitors of and are merged to generate a1/2shift on plates.If,the necessary1/4shift on top plates is accomplished by split-ting the2C in and and switching them to0and,respectively.Nevertheless,If
,the required1/4shift on top plates is accomplished by merging the2C in and.The same procedure is conducted until the bit is resolved.
The quantitative energy consumption of CAS and MS methods in each switching step is also shown i
n the Fig.3.In the most energy-wasting switching(first step switching),the MS switching applies merging operation instead of switching the2C to and0,respectively,and the energy consumption is instead of.In the following switching step, either the merging operation or the new introduced splitting operation is employed to accomplish successive approximation. For an n-bit SAR ADC,if the probability of each digital output code is equal,the average switching energy of conven-tional[3],CAS[2],monotonic[3],-based[4]methods can be derived as
(1)
(2)
(3)
(4) The average switching energy for an n-bit SAR ADC using the proposed MS switching procedure can be derived as
(5) However,the CAS and MS switching consume reset energy, which can be derived as
(6) For a10-bit case,the CAS,set-and-down,and-based switching procedures consume88.6,255.5and170.2, respectively,while the proposed MS switching consumes only21.6.Alth
ough the CAS and MS switching methods energy than the monotonic and-based switching methods during the conversion phase,they must be pre-charged at the sampling phase and consume reset energy,which is255.5.Fig.4shows the
Fig.3.(a)A4-bit conversion example of the CAS DAC switching method.(b)A4-bit conversion example of the proposed MS DAC switching method. switching energy curves versus output code of MS switching
and the other well-known techniques including both sampling
Compared to set-and-down(255.5)and CAS(344.1
)techniques,MS(233.9)switching consumes
8.5%and32%less energy,respectively.It also solves the
common-mode voltage variation issue of set-and-down and
hence obviates the distortion at conversion phase.Although
-based switching(170.2)is the most energy-efficient
among all techniques,realizing the required extra reference
voltage()at0.3V is arduous.Considering the required
unit capacitors,MS switching is the same as the other methods
and is half of the conventional one.
Assuming the bottom-plate voltage of the being switched ca-
pacitor on the p-side is and the one on the n-side is
,as shown in Fig.5(a).merging operation,assuming
Fig.4.Switching energy versus output code.
TABLE I
C OMPARISON OF
D IFFERENT S WITCHING P
ROCEDURES
Fig.5.DAC switching voltage (a)before merging operation.(b)After merging operation.
the capacitor is equal to ,the voltages on both
bootstrappedside then can be as
(7)
,where is the sum of total capacitors
.Hence,the voltage change on top plates
is
(8)
Considering the
noise,assuming the is disturbed by noise and becomes before operation,then the merged voltage would have shift from ideal value,making input voltage shift of
(9)
However,the voltage change on top plates is still the same as ideal case.That is,the reference voltage variation only causes input common-mode voltage variation during merging operation.Then considering the splitting operation,the is splitting first and the and are connected to constant voltages,respectively to Fig.5(a)].The common-mode voltage shift caused by merging operation is erased and be-comes the same as the condition before merging operation.In addition,to reduce comparator input common-mode voltage variation,the
switch sizes of on both sides are designed the same to cancel out the charge-injection and clock feedthrough effects.
During comparison phase,the noise would couple to the comparator input via DAC array and the mount depends on
Fig.6.DAC array of the proposed MS switching.
the number of capacitors connected to .Therefore,different switching sequence would induce different noise pro file.Taking the proposed MS switching as an example,at first comparison the noise on the top plates is 0,because the noises on p-side and n-side are common-mode and canceled out,as shown in Fig.3(b).At second comparison,if
,the noise on the top plates is .
Nevertheless,if ,the noise on the top becomes .However,by care-fully examining the switching CAS and MS tech-niques,as shown in Fig.3,each switching step has the same
noise.This is true for -base and monotonic as well.Hence,the linearity degradation due to noise is the same for all these switching methods.Besides the noise,the mismatch of capacitive DAC array is a main error source which deteriorates ADC linearity.For matching concerns,a large capacitor in the DAC array is usually composed of multiple identical unit capacitors.Due to process variation,the practical capacitance of each unit capacitor devi-ates from the nominal value.Suppose the unit capacitor is mod-eled with a nominal value of and a standard deviation of .Therefore,for n-bit ADC with MS switching,the capacitance of each capacitor,shown in Fig.6can be expressed as:
(10)
where i is an integer representing the bit position,
is the unit capacitance and is the error term.Assuming that the error dis-tributions of unit capacitors are independent and identically dis-tributed (i.i.d.)Gaussian random variables,the mean and vari-ance of the error terms are
(11)
The differential input voltage of the comparator before it makes the last decision (i.e.,all bits are decided except the LSB)can be expressed as
(12)
where
is the digital estimation,represents the comparator decision for the nth bit (or 1),is
the input signal difference,and is the reference voltage. Subtracting the nominal value yields the error INL
(13) with variance
(14) For the proposed MS switching procedure,MSB is determined mismatch-independently,and worst cases INL occur at the VFS/4and3VFS/4,where VFS means the full scale signal.At these two transitions,the most capacitors are switched.Therefore,the variance of maximum INL error is derived as
(15) Therefore,the maximum INL of MS switching is
(16) The DNL is the difference of two adjacent codes expressed as
(17) The maximum DNL of MS switching is the code distance between the middle code transition and its previous one.The error term of middle code is generated at the MSB decision and it is error free with top-plate sampling.Therefore,the variance of the maximum DNL error is derived
as Fig.7.Static performance with a SAR ADC using CAS switching method and MS switching method.
(18)
Therefore,the maximum DNL of MS switching is
(19) The same derivation procedures are applied to CAS switching,and the maximum INL and DNL can be expressed as(20)and(21).
(20)
(21) To verify the theoretical analysis above,behavioral simu-lations for a10-bit SAR ADC with CAS and MS switching were developed.The only error source is the random mismatch of capacitors and each capacitor cell has a Gaussian random error with a standard deviation of3%.Fig.7shows the root-mean-square(rms)of DNL and INL of10000Monte-Carlo runs.As expected,the worst DNL is at the middle code and the worst INL occurs at the VFS/4and3VFS/4for both CAS and MS switching.The DNL of MS switching is better than CAS switching by a factor of and the INL by a factor of. Therefore,for the same peak DNL and INL,MS switching can use smaller unit capacitor than CAS switching.
III.I MPLEMENTATION OF K EY B UILDING B LOCKS
The fundamental building blocks of the proposed MS switching ADC are two S/H circuits,a dynamic comparator, SAR control logics,and two capacitive DAC networks.The de-tailed design consideration of the building blocks are described in the following subsections.
A.Double-Bootstrapped Sample-and-Hold
The double-bootstrapped switch shown in Fig.8performs the S/H function.With the bootstrapped switch,the gate-source voltage of the sampling transistors(and)arefixed at the double supply voltage,which makes the on-resistance a small constant value and thus improves the switch linearity. When is high,and are pre-charged to VDD.After becomes low,and are connected in series by a low threshold PMOS to improve boosting speed.The transient

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