V IN , V OUT , SWA, .–0.3 to 6V SWA, SWB Voltage, Pulsed, <100ns .........................7V SHDN, VC Voltage .........................................–0.3 to 6V FB Voltage ...................................–0.3 to (V OUT  + 0.3V)Operating Temperature Range (Note 2)..–40°C to 85°C Storage –65°C to 125°C
ORDER PART NUMBER DD PART MARKING T JMAX  = 125°C, θJA  = 45°C/W,
θJC  = 3°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LBBG
ABSOLUTE AXI U  RATI GS
W W W
U PACKAGE/ORDER I FOR ATIO
U
U
W (Note 1)
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: The LTC3428E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation with statistical process controls.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T A  = 25°C. V IN  = 3.3V, V OUT  = 5V unless otherwise noted.
PARAMETER
CONDITIONS MIN TYP MAX UNITS
Minimum Startup Voltage    1.5  1.6V Quiescent Current, V OUT SHDN = V IN 100200µA Quiescent Current, V IN SHDN = V IN    1.3
2.0mA Shutdown Current SHDN = 0V 1µA Switching Frequency Per Phase ●0.8  1.0  1.2MHz FB Regulated Voltage ●
1.219
1.243  1.268V FB Input Current
V FB  = 1.24V
150nA Error Amp Transconductance 170
µS Output Adjust Voltage    1.6
5.25
V NMOS Switch Leakage V SWA , V SWB  = 5.5V, Per Phase 0.1  2.5
µA NMOS Switch On Resistance V OUT  = 5V, Per Phase 0.093
ΩNMOS Current Limit Per Phase
●2  2.5A
SHDN Input Threshold ●
0.40.8  1.5V SHDN Input Current 0.011µA Maximum Duty Cycle ●80
87
%Minimum Duty Cycle ●
%Current Limit Delay to Output
(Note 3)
40
ns
Note 3: Specification is guaranteed by design and not 100% tested in production.
Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.Continuous operation above the specified maximum operating junction temperature may impair device reliability.
TOP VIEW
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN EXPOSED PAD MUST BE SOLDERED
TO GROUND PLANE ON PCB 10967845
321PGNDB SWB V IN AGND FB
PGNDA SWA V OUT SHDN V C
11
LTC3428EDD
3428 G04
3428 G02
3428 G01
3428 G03
3428 G07
10ns/DIV
500ns/DIV
500ns/DIV
500ns/DIV
100µs/DIV
Output Voltage Ripple with 22µF
PI  FU CTIO S
U U U
PGNDA, PGNDB (Pins 1, 10, 11 (Exposed Pad)): Power Ground for the IC. Tie directly to local ground plane.SWB (Pin 2), SWA (Pin 9): Phase B and Phase A Switch Pins. The inductor and Schottky diodes for each phase are connected to these pins. Minimize trace length to reduce EMI.
V OUT  (Pin 3): Power Supply Output and Bootstrapped Power Source for the IC. Connect low ESR output filter capacitors from this pin to the ground plane.
SHDN (Pin 4): Shutdown Pin. Grounding this pin shuts down the IC. Connect to a voltage greater than 1.5V to enable.
TYPICAL PERFOR  A  CE CHARACTERISTICS
U W
P E A K  C U R R E N T  L I M I T  (A )
3.43.2
3.02.82.62.42.22.03428 G10
TEMPERATURE (°C)
–45
1555–25
–5
357595
Peak Current Limit vs Temperature
V C  (Pin 5): Error Amp Output. A frequency compensation network is connected to this pin to compensate the boost converter loop.
FB (Pin 6): Feedback Pin. A resistor divider from V OUT  is connected here to set the output voltage according to V OUT  = 1.243 • (1 + R1 / R2)
AGND (Pin 7): Signal Ground for the IC. Connect to ground plane near feedback resistor divider.
V IN  (Pin 8): Input Supply Pin. Bypass V IN  with a low ESR ceramic capacitor of at least 4.7µF. X5R and X7R dielec-trics are preferred for their superior voltage and tempera-ture characteristics.
>bootstrapped

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