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a
ADP3412
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 www.analog Fax: 781/326-8703© Analog Devices, Inc., 2002
Dual MOSFET Driver with Bootstrapping
FUNCTIONAL BLOCK DIAGRAM
IN
FEATURES
All-In-One Synchronous Buck Driver Bootstrapped High Side Drive
One PWM Signal Generates Both Drives Programmable Transition Delay
Anticross-Conduction Protection Circuitry APPLICATIONS
Multiphase Desktop CPU Supplies
Mobile Computing CPU Core Power Converters Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
C DLY
Figure 1.General Application Circuit
GENERAL DESCRIPTION
The ADP3412 is a dual MOSFET driver optimized for driving two N-channel MOSFETs which are the
two switches in a nonisolated synchronous buck power converter. Each of the drivers is capable of driving a 3000pF load with a 20ns propa-gation delay and a 30ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with “floating ” high side gate drivers. The ADP3412 includes overlapping drive protection (ODP) to pre-vent shoot-through current in the external MOSFETs.bootstrapped
ADP3412–SPECIFICATIONS1
(T A = 0؇C to 70؇C, VCC = 5 V, BST = 4 V to 26 V, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit
SUPPLY
Supply Voltage Range VCC  4.15  5.07.5V Quiescent Current ICC Q12mA PWM INPUT
Input Voltage High2  2.0V Input Voltage Low20.8V HIGH SIDE DRIVER
Output Resistance,Sourcing Current V BST– V SW = 4.6 V  2.55ΩOutput Resistance,Sinking Current V BST– V SW = 4.6 V  2.55ΩTransition Times3 (See Figure 2)tr DRVH, tf DRVH V BST – V SW = 4.6 V, C LOAD = 3 nF2035ns Propagation Delay3, 4 (See Figure 2)tpdh DRVH V BST– V SW
= 4.6 V1020Note5ns
tpdl DRVH V BST – V SW = 4.6 V25ns LOW SIDE DRIVER
Output Resistance,Sourcing Current VCC = 4.6 V  2.55ΩOutput Resistance,Sinking Current VCC = 4.6 V  2.55ΩTransition Times3 (See Figure 2)tr DRVL, tf DRVL VCC = 4.6 V, C LOAD = 3 nF2035ns Propagation Delay3, 4 (See Figure 2)tpdh DRVL VCC = 4.6 V30ns
tpdl DRVL VCC = 4.6 V25ns
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).
3AC specifications are guaranteed by characterization but not production tested.
4For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
5Maximum propagation delay = 40 ns + (1 ns/pF ϫ C
).
DLY
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +8 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +8 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–5.0 V to +25 V
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
–2–REV. A
ADP3412
–3–
REV. A
PIN FUNCTION DESCRIPTIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3412 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ADP3412
Figure 2.Nonoverlap Timing Diagram
(Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
–4–REV. A
V O L T A G E
TIME – ns
TPC 1.DRVH Fall and DRVL Rise Times AMBIENT TEMPERATURE – ؇C
3025
85
25
T I M E  – n s
5075201510535RISE TIME
FALL TIME
VCC = 5V C LOAD  = 3nF
TPC 4.DRVL Rise and Fall Times vs.Temperature
JUNCTION TEMPERATURE – ؇C
30
2500
25T I M E  – n s
5075tpdl DRVH
VCC = 5V C LOAD  = 3nF tpdl DRVL
20
15
105100125
TPC 7.Propagation Delay vs.Temperature
Typical Performance Characteristics–ADP3412
–5–
REV. A
V O L T A G E
TIME – ns
TPC 2.DRVL Fall and DRVH Rise Times
CAPACITANCE – nF
40
6
1
T I M E  – n s
2345
VCC = 5V T A  = 25؇C 30
20
10
DRVH
DRVL
TPC 5.DRVH and DRVL Rise Times vs. Load Capacitance
IN FREQUENCY – kHz
400
S U P P L Y  C U R R E N T  – m A
35
2015105302501200
200
4006008001000VCC = 5V T A  = 25؇C C LOAD  = 3nF
TPC 8.Supply  Current vs.Frequency
JUNCTION TEMPERATURE – ؇C
3025
85
25T I M E  – n s
507520
15
10
5RISE TIME
FALL TIME
VCC = 5V C LOAD  = 3nF
TPC 3.DRVH Rise and Fall Times vs.Temperature
CAPACITANCE – nF
350T I M E  – n s
3025
2015105
1
23456
VCC = 5V T A  = 25؇C
DRVH
DRVL
TPC 6.DRVH and DRVL Fall Times vs. Load Capacitance
JUNCTION TEMPERATURE – ؇C
11.0
10.5
9.0
125
25S U P P L Y  C U R R E N T  – m A
507510010.0
9.5
VCC = 5V f IN  = 250kHz C LOAD  = 3nF
TPC 9.Supply Current vs.Temperature

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