A10-bit1-GS/s CMOS ADC with FOM=70fJ/Conversion
Sedigheh Hashemi and Behzad Razavi
bootstrappedElectrical Engineering Department
University of California,Los Angeles
Abstract A pipelined ADC incorporates a precharged resistor-ladder DAC in a multi-bit front-end,achieving fast settling and allowing calibrationof both dynamic and static gain errors.Using simple differential pairs with a gain of 5as op amps and realized in65-nm CMOS technology,the 10-bit ADC consumes36mW at a sampling rate of1GHz and exhibits an SNDR of52.7dB at an input frequency of 490MHz.
I.I NTRODUCTION
The f gure of merit(FOM)of ADCs tends to degrade as higher speeds and/or resolutions are sought.For example,the FOM rises from6.3fJ/conversion for an8-bit,1.1-MHz ADC [1]to about500fJ/conversion for a12-bit3-GHz design[2]. It is therefore desirable to develop low-power gigahertz ADCs in the resolution range of10to12bits.
This paper proposes a pipelined ADC architecture employ-ing a precharged resistor-ladder digital-to-analog converter (DAC)and a multi-bit front end with a low-gain op amp. Avoiding the need for op amp nonlinearity calibration,the ADC only computes the gain error at high speeds and corrects it in the digital domain.
Section II describes our design approach and the resulting ADC architecture.Section III deals with the design of build-ing blocks and Section IV presents the experimental results obtained from the prototype.
II.P ROPOSED ADC A RCHITECTURE
A.General Considerations
The performance of pipelined ADCs is determined by pri-marily that of the op amps used in their f rst few stages.Among the imperfections aff icting these op amps,the f nite gain and the nonlinearity have been the target of numerous calibration techniques.However,the nonlinearity poses diff cult chal-lenges:foreground calibration may not adequately hold as the temperature varies,and background calibration restricts the input signal bandwidth or dynamic range,does not correct for capacitor mismatch,or requires a slow but accurate auxiliary ADC[3]-[5].These issues are summarize
d in[6].
It is desirable to architect the ADC such that the stages inherently avoid nonlinearity.To this end,the ADC can resolve several bits in the front end,thus allowing the f rst multiplying DAC(MDAC)to operate with small output swings.Such swings also improve the settling speed of the MDAC.What remains to be corrected is the gain error arising from the f nite gain of the op amp and capacitor mismatches.If possible,the gain error due to the MDAC’s incomplete settling should also be calibrated.
While attractive,multi-bit front ends entail another issue: if the multi-bit DAC in the f rst stage incorporates capacitors, then the mismatch between each of these capacitors and the MDAC feedback capacitor must be computed and corrected. We may instead consider a resistor-ladder DAC(RDAC),given that such DACs can achieve linearities exceeding11bits([6]). However,it is generally believed that resistor-ladder DACs are slow,a true statement for stand-alone designs.Nonetheless, our key observation here is that,in a pipelined ADC environ-ment,the DAC output node can be precharged to the analog input level,thereby considerably relaxing the settling speed.
B.ADC Architecture
Fig.1(a)shows the f rst stage of the ADC architecture fol-lowed by the back end.A4-bit sub-ADC in the f rst stage along with an MDAC gain of2greatly simplif es the design of the op amp.Moreover,a precharged resistor-ladder DAC rapidly establishes the analog equivalent of the sub-ADC output at node.One bit of redundancy accommodates various errors, including the offsets of the comparators in the sub-ADC and the timing mismatch between the sub-ADC and the MDAC. The operation of the front end and the timing budgets thereof are explained with the aid of the waveforms shown in Fig.1(b). For25%of the clock period(250ps),bootstrapped switches sample the analog signal on the RDAC output[node in Fig.1(a)],the input capacitor of the MDAC,and the input capacitors of the sub-ADC comparators.Next,the sub-ADC is clocked while is held,The coarse digital estimate arrives after250ps,turning on one switch in the RDAC and driving to the corresponding value.The last500ps of the clock period is allocated to the settling of and the MDAC output, 1
.
The back end of the ADC consists of eight1.5-bit stages, the f rst four of which are scaled down by a factor of two.
III.B UILDING B LOCKS
A.Front-End Stage
To save power,the front end employs a single high-speed resistor ladder to provide three sets of quantities:(1)reference taps for the f rst sub-ADC,(2)f rst stage RDAC voltages,and
978-1-4673-1556-2/12/$31.00@2012 IEEE
(c)
V V 1
V 2
V 31V 32
(b)
V X V res1
Clock
Fig.1.(a)Front-end stage employs a precharged RDAC and a gain of 2
to improve linearity and speed,(b)conceptual DAC and residue waveforms,and (c)reference ladder structure.
(3)high-precision voltages for foreground calibration of the ADC.As such,the design of the ladder and its associated circuitry plays a critical role in the overall performance.It is important to note that the fast settling of the ladder also allows performing calibration at a high sampling rate and hence correcting for incomplete settling of the MDAC.
The reference ladder [Fig.1(c)]is realized as a continuous rectangular geometry made of silicided polysilicon,with its taps positioned on the edge to minimally disturb the current f ow [6].This ladder ha
s a total resistance of 150W ,which translates to a worst-case Thevenin equivalent of 37.5W ,neg-ligibly affecting the RDAC settling and making the resistance of the DAC switches dominant.According to simulations,the worst-case time constant at node is equal to 30ps.
Fig.2.Effect of sub-ADC kickback noise on the reference ladder.
B.Sub-ADC Kickback Noise
A critical issue in sharing a single ladder between the sub-ADC and the DAC is that the kickback noise of the former may substantially disturb the tap voltages utilized by the latter.It is therefore essential that the disturbance decays rapidly.This design employs a StrongArm comparator for low power consumption,but must deal with its large kickback noise.Fig.2illustrates the kickback noise mechanism.When goes high,and are at ,and one falls toward ground,coupling through the gate-drain capacitance of 1or 2and drawing a current from the ladder.Since for most of the 15comparators in the sub-ADC,the change in is much larger than in (or vice versa),the kickback noise contains a high differential component.
To remedy this effect,transistors 3and 4are added so that the large change in or is coupled to both inputs.In other words,most of the differential error is converted to a common-mode error.Simulations i
ndicate that the kickback noise due to the sub-ADC creates a peak jump of 2.5mV on the differential voltages produced by the ladder and decays in about 30ps.That is,by 2in Fig.1(b),the ladder voltages safely settle to their static values.
The multi-bit operation results in a peak single-ended swing of only 75mV at the output of the MDAC.The MDAC op amp is therefore implemented as a simple differential pair with resistor loads and an open-loop gain of 5.A tail current of 3mA affords fast settling.
C.High-Speed Calibration
Foreground calibration is performed by applying to the ADC f ve differential dc voltages provided by the ladder:zero,
32,and 232.In a manner similar to that
described in [6],calibration begins from stage 6and proceeds backwards.Note that dynamic gain errors are calibrated even though the input in each case is constant because the MDAC outputs must start from zero and settle anew each time.
2
IV.M EASUREMENT R ESULTS
The prototype ADC has been fabricated in65-nm digital CMOS technology.Shown in Fig.3is the die active area, which measures250m700m.The ADC reference volt-ages are provided externally and the calibration is performed off-chip.Careful simulations including bond wire inductance reveal that and in Fig.1(a)must have no bypass capacitors so that they can quickly recover from the switching action of the DAC.
The maximum differential nonlinearity(DNL)and integral nonlinearity(INL)reach2LSB and6LSB,respectively,before gain error calibration.Fig.4plots the calibrated DNL and INL for a sampling rate of1GHz.To demonstrate the eff cacy of calibration at high clock rates,two cases are investigated:the calibration itself is performed at100MHz[Fig.4(a)],or at 700MHz[Fig.4(b)].We observe that the maximum DNL and INL respectively fall from1.4LSB and3LSB to0.74 LSB and1.4LSB when calibration is performed at700MHz. These results suggest that the MDAC in the f rst stage(and possibly second stage)exhibits incomplete settling and greatly benef ts from calibration at a high clock frequency.Note that only the gain error of each stage is calibrated.
Fig.5plots the measured output spectrum for input frequen-cies of1.7MHz and490MHz at a sampling
rate of1GS/s. The third-order harmonic at635dB in the former case con-f rms the high linearity provided by the resistor ladder.The signal-to-(noise+distortion)ratio(SNDR)is possibly limited by ringing on the reference lines.
The dynamic performance of the ADC is shown in Fig.6 for a sampling rate of1GS/s and analog input frequencies up to490MHz.The SNDR varies from57dB to52.7dB. The spurious-free dynamic range(SFDR)is also measured and observed to vary from63.5dB to60dB in this frequency range.
The ADC draws36mW from a1.2-V supply,of which2.5 mW is consumed by the reference ladder,14.4mW by the op amps,and18mW by the clock tree and the pipeline alignment latches.Computed as36mW/(2460MHz2),the f gure of merit is70fJ/conversion.A less conservative clock tree design could improve the FOM considerably.
Table I summarizes the measured performance of the ADC and Fig.7expands the FOM plot in[7]to include our work. Note that the design reported in[7]is realized in40-nm tech-nology and,due to time-interleaving,may suffer from a large input capacitance.Moreover,the design relies on the raw de-vice matching of the technology and does not calibrate the gain error.
V.C ONCLUSION
Pipelined ADCs can greatly benef t from the use of multi-bit front ends that incorporate precharged resistor-ladder DACs. With the settling speed afforded by the low-resistance lad-der,the ADC can be calibrated at high sampling rates,thus correcting for the incomplete settling of the MDACs.In ad-dition,RDACs simplify the calibration logic by reducing the
Fig.4.Measured DNL and INL at=1GS/s with gain error calibration run at(a)100MHz and(b)700MHz.
required correction to only that of the gain error.Utilizing these concepts,a10-bit1-GS/s ADC has been demonstrated that improves the FOM by a factor of2.6with respect to the state of the art.
Acknowledgment
The authors thank B.D.Sahoo for valuable discussions.This research was supported by the DARPA HEALICs program and Realtek Semiconductor.The authors gratefully acknowledge
the TSMC University Shuttle Program for chip fabrication.
R EFERENCES
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=490MHz (down-sampled by a factor of 16).
GS/s.
TABLE I
ADC Performance Summary

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