FAN7888  — 3 Half-Bridge Gate-Drive IC
3 Half-Bridge Gate-Drive IC
Features
Floating Channel for Bootstrap Operation to +200V  Typically 350mA/650mA Sourcing/Sinking Current Driving Capability for All Channels  3 Half-Bridge Gate Driver
Extended Allowable Negative V S  Swing to -9.8V for Signal Propagation at V BS =15V
Matched Propagation Delay Time Maximum 50ns  3.3V and 5V Input Logic Compatible
Built-in Shoot-Through Prevention Circuit for All Channels with Typically 270ns Dead Time
Built-in Common Mode dv/dt Noise Canceling Circuit
Built-in UVLO Functions for All Channels
Applications
3-Phase Motor Inverter Driver
Description
The FAN7888 is a monolithic three half-bridge gate-drive IC designed for high-voltage, high-speed driving MOS-FETs and IGBTs operating up to +200V.
Fairchild’s high-voltage process and common-mode noise canceling technique provide stable operation of high-side drivers under high-dv/dt noise circumstances.An advanced level-shift circuit allows high-side gate driver operation up to V S  = -9.8V (typical) for V BS  =15V. The UVLO circuits prevent malfunction when V DD  and V BS  are lower than the specified threshold voltage. Output drivers typically source/sink 350mA/650mA,respectively, which is suitable for three-phase half-bridge applications in motor drive systems.
Ordering Information
All packages are lead free per JEDEC: J-STD-020B standard.
20-SOIC
Part Number
Package
Operating Temperature Range
Packing Method
FAN7888M 20-SOIC
-40°C to +125°C
Tube FAN7888MX
Tape & Reel
FAN7888  — 3 Half-Bridge Gate-Drive IC
Figure 1. 3-Phase BLDC Motor Drive Application
Internal Block Diagram
U
V
W
UU UL
VU VL
WU WL
Q4
Q6
Q2
Q1Q3Q5
Q1Q3Q5
Q4Q6Q2
3-Phase Inverter
GND LO3LIN1V DD V S1HO1V B1
HIN1V S2HO2V B2V S3HO3V B3
HIN2HIN3LIN2LIN3
LO2
LO12019
18171615
1413
1212
3456
78
910
V S1V S3
V S2V S2
V S3
V S1
FAN7888
3-Phase
BLDC Motor Controller I U
I V
I W
11
FAN7888 Rev.00
UVLO
R R S
Q
DELAY
DRIVER
DRIVER
V  Phase  Driver
U Phase Driver
LO2
V S2HO2V B2
HO3V B3
UHIN
ULIN
V DD
VHIN V DD VDD_UVLO
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
VLIN
SCHMITT TRIGGER INPUT
SHOOT-THOUGH PREVENTION
CONTROL LOGIC
UVLO
VDD
V DD
LO1
GND
V S1
HO1
V B1
NOISE CANCELLER
PULSE GENERATOR
FAN7888  — 3 Half-Bridge Gate-Drive IC
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1HIN1Logic input 1 for high-side gate 1 driver 2LIN1Logic input 1 for low-side gate 1 driver 3HIN2Logic input 2 for high-side gate 2 driver 4LIN2Logic input 2 for low-side gate 2 driver 5HIN3Logic input 3 for high-side gate 3 driver 6LIN3Logic input 3 for low-side gate 3 driver 7LO3Low-side gate driver 3 output
8V S3High-side driver 3 floating supply offset voltage 9HO3High-side driver 3 gate driver output 10V B3High-side driver 3 floating supply voltage 11GND Ground
12V DD Logic and all low-side gate drivers power supply voltage 13LO2Low-side gate driver 2 output
14V S2High-side driver 2 floating supply offset voltage 15HO2High-side driver 2 gate driver output 16V B2High-side driver 2 floating supply voltage 17LO1Low-side gate driver 1 output
GND
LO3FAN7888
V DD V S1
HIN2HIN3LIN2LIN3LO2LO118171615141312113
45678
910
V S2HO2V B2V S3
HO3V B3FAN7888 Rev.00
FAN7888  — 3 Half-Bridge Gate-Drive IC
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T A =25°C, unless otherwise specified.
Notes:
1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
2. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection      JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.3. Do not exceed P D  under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
V B High-side Floating Supply Voltage of V B1,2,3-0.3225.0V V S High-side Floating Supply Offset Voltage of V S1,2,3V B1,2,3-25V B1,2,3+0.3V V HO1,2,3High-side Floating Output Voltage V S1,2,3-0.3V B1,2,3+0.3V V DD Low-side and Logic-fixed Supply Voltage -0.325.0V V LO1,2,3Low-side Output Voltage
-0.3V DD +0.3V V IN Logic Input Voltage (HIN1,2,3 and LIN1,2,3)-0.3
V DD +0.3V dV S /dt Allowable Offset Voltage Slew Rate 50V/ns P D Power Dissipation (1)(2)(3)
1.8W θJA Thermal Resistance, Junction-to-ambient 80 °C/W T J Junction Temperature +150
°C T S
Storage Temperature
-55+150
°C
Symbol
Parameter
Min.
Max.
Unit
V B1,2,3High-side Floating Supply Voltage V S1,2,3+10V S1,2,3+20
V V S1,2,3High-side Floating Supply Offset Voltage 6-V DD 200V V DD Supply Voltage
1020V V HO1,2,3High-side Output Voltage V S1,2,3  V B1,2,3V V LO1,2,3Low-side Output Voltage
GND V DD V V IN Logic Input Voltage (HIN1,2,3 and LIN1,2,3)GND  V DD V T A
Ambient Temperature
-40
+125
°C
FAN7888  — 3 Half-Bridge Gate-Drive IC
Electrical Characteristics
V BIAS (V DD , V BS1,2,3) = 15.0V, T A = 25°C, unless otherwise specified. The V IN  and I IN  parameters are referenced to GND. The V O  and I O  parameters are referenced to GND and V S1,2,3 and are applicable to the respective outputs LO1,2,3 and HO1,2,3.
Note:
4. This parameter is guaranteed by design.
Symbol
Characteristics
Condition
Min.Typ.Max.Unit
LOW SIDE POWER SUPPLY SECTION
I QDD Quiescent V DD  Supply Current
V LIN1,2,3=0V or 5V 160350µA I PDD1,2,3Operating V DD  Supply Current for each Channel
f LIN1,2,3=20kHz, rms Value 500900µA V DDUV+V DD Supply Under-Voltage Positive-goin
g Threshold
V DD =Sweep, V BS =15V
7.28.29.0V V DDUV-V DD Supply Under-Voltage Negative-going
Threshold
V DD =Sweep, V BS =15V
6.8
bootstrapped
7.88.5
V V DDHYS
V DD Supply Under-Voltage Lockout Hysteresis
V DD =Sweep, V BS =15V
0.4
V
BOOTSTRAPPED POWER SUPPLY SECTION I QBS1,2,3Quiescent V BS  Supply Current for each Channel
V HIN1,2,3=0V or 5V 50120µA I PBS1,2,3Operating V BS  Supply Current for each Channel
f HIN1,2,3=20kHz, rms Value 400800µA V BSUV+V BS  Supply Under-Voltage Positive-goin
g Threshold
V DD =15V, V BS =Sweep
7.28.29.0V V BSUV-V BS  Supply Under-Voltage Negative-going
Threshold
V DD =15V, V BS =Sweep
6.8
7.88.5
V V BSHYS V BS  Supply Under-Voltage Lockout Hysteresis
V DD =15V, V BS =Sweep 0.4
V I LK Offset Supply Leakage Current V B1,2,3=V S1.2.3=200V
10µA GATE DRIVER OUTPUT SECTION
V OH High-level Output Voltage, V BIAS -V O I O =20mA 1.0V V OL Low-level Output Voltage, V O
I O =20mA
0.6
V I O+Output HIGH Short-circuit Pulsed Current (4)V O =0V, V IN =5V with PW<10µs 250
350mA I O-Output LOW Short-circuit Pulsed Current (4)V O =15V, V IN =0V with PW<10µs 500
650mA
V S
Allowable Negative V S  Pin Voltage for IN Signal Propagation to H O -9.8
-7.0
V
LOGIC INPUT SECTION (HIN, LIN)
V IH Logic "1" Input Voltage    2.5
V V IL Logic "0" Input Voltage    1.0V I IN+Logic "1" Input Bias Current V IN =5V 25
50µA I IN-Logic "0" Input Bias Current (4)V IN =0V
2.0µA R IN Input Pull-down Resistance
100
200
300
K Ω

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