This is a product that has fixed target specifications but are subject Ramtron International Corporation
to change pending characterization results.  1850 Ramtron Drive, Colorado Springs, CO 80921
FM24C64B
64Kb Serial 5V F-RAM Memory
Features
64K bit Ferroelectric Nonvolatile RAM  • Organized as 8,192 x 8 bits
• High Endurance 1 Trillion (1012) Read/Writes  • 38 Year Data Retention • NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
• Up to 1 MHz maximum bus frequency • Direct hardware replacement for EEPROM • Supports legacy timing for 100 kHz & 400 kHz
Low Power Operation • 5V operation
• 100 µA Active Current (100 kHz) •    4 µA (typ.) Standby Current
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C • 8-pin “Green”/RoHS SOIC (-G)
Description
The FM24C64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.
The FM24C64B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling.  The FM24C64B is capable of supporting 1012 read/write cycles, or a million times more write cycles than EEPROM.
These capabilities make the FM24C64B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writes with less overhead for the system.
The FM24C64B provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24C64B is available in an industry standard 8-pin SOIC package and uses a familiar two-wire protocol. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C.  Pin Configuration
A0A1A2VSS
VDD WP SCL SDA
Pin Names Function
A0-A2 Device Select Address SDA Serial Data/address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage
Ordering Information
FM24C64B-G “Green”/RoHS 8-pin SOIC FM24C64B-GTR “Green”/RoHS 8-pin SOIC, Tape & Reel
Figure 3. Data Transfer Protocol
Stop Condition
A Stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations must end with a Stop condition. If an operation is pending when a stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a Stop condition.
Start Condition
A Start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high. All read and write transactions begin with a Start condition. An operation in progress can be aborted by asserting a Start condition at any time. Aborting an operation using the Start condition will ready the FM24C64
B for a new operation.
If during operation the power supply drops below the specified V DD minimum, the system should issue a Start condition prior to performing another operation Data/Address Transfer
All data transfers (including addresses) take place while the SCL signal is high. Except under the two conditions described above, the SDA signal should not change while SCL is high.
Acknowledge
The Acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter should release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, the condition is a No-Acknowledge and the operation is aborted. The receiver could fail to acknowledge for two distinct reasons. First, if a byte transfer fails, the No-Acknowledge ends the current operation so that the device can be addressed again. This allows the last byte to be recovered in the event of a communication error. Second and most common, the receiver does not acknowledge the data to deliberately end an operation. For example, during a read operation, the FM24C64B will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM24C64B to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command.
Slave Address
The first byte that the FM24C64B expects after a start condition is the slave address. As shown in Figure 4, the slave address contains the Slave ID (device type), the device select address bits, and a bit that specifies if the transaction is a read or a write. Bits 7-4 define the device type and must be set to 1010b for the FM24C64B. These bits allow other types of function types to reside on the 2-wire bus within an identical address range. Bits 3-1 are the select bits which are equivalent to chip select bits. They must match the corresponding value on the external address pins to select the device. Up to eight FM24C64Bs can reside on the same two-wire bus by assigning a different address to each. Bit 0 is the read/write bit. A 1 indicates a read operation, and a 0 indicates a write.
1010A2A1A0R/W Slave ID Device Select
7
6
pending5
4
3
2
1
Figure 4. Slave Address
Addressing Overview
After the FM24C64B (as receiver) acknowledges the device address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The first is the MSB (upper byte). Since the device uses only 13 address bits, the value of the upper three bits are don’t care. Following the MSB is the LSB (lower byte) with the remaining eight address bits. The address value is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch, either a newly written value or the address following the last access. The current address will be held as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below.
After transmission of each data byte and just prior to the acknowledge, the FM24C64B increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing externally. After the last address (1FFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation.
Data Transfer
After the address information has been transmitted, data transfer between the bus master and the FM24C64B can begin. For a read operation, the FM24C64B will place 8 data bits on the bus then wait for an Acknowledge from the master. If the Acknowledge occurs, the FM24C64B will transfer the next sequential byte. If the Acknowledge is not sent, the FM24C64B will end the read operation. For a write operation, the FM24C64B will accept 8 data bits from the master and then send an Acknowledge. All data transfer occurs MSB (most significant bit) first.  Memory Operation
The FM24C64B is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of FRAM technology. These improvements result in some differences between the FM24C64B and a similar co
nfiguration EEPROM during writes. The complete operation for both writes and reads is explained below.
Write Operation
All writes begin with a device address, then a memory address. The bus master indicates a write operation by setting the LSB of the device address to a 0. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 1FFFh to 0000h.
Unlike other nonvolatile memory technologies, there is no write delay with FRAM. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including a read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a ready condition.
Internally, the actual memory write occurs after the 8th  data bit is transferred. It will be complete before the Acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using a Start or Stop condition prior to the 8th  data bit. The F
M24C64B uses no page buffering.
Portions of the memory array can be write protected using the WP pin. Pulling the WP pin high (V DD ) will write-protect addresses in the upper quadrant from 1800h to 1FFFh. The FM24C64B will not acknowledge data bytes that are written to protected addresses. In addition, the address counter will not increment if writes are attempted to these addresses. Pulling WP low (V SS ) will deactivate this feature. WP should not be left floating.
Figures 5 and 6 illustrate both a single-byte and multiple-byte write cases.

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