MLCC APPLICATION GUIDE
No. Process Condition
1 Operating
Condition
(Storage) 1) The capacitor must be stored in an ambient temperature between 5 ~ 40℃ with a relative humidity of
20 ~ 70%. The products should be used within 6 months upon receipt.
2) The capacitors must be operated and stored in an environment free of dew condensation and these
gases such as Hydrogen Sulphide, Hydrogen Sulfate, Chlorine and Ammonia and sulfur.
3) Avoid storing in direct sunlight and falling of dew.
4) Do not use capacitors under high humidity and high and low atmospheric pressure which may affe
ct capacitors reliability.
2 Circuit
design
Caution 2-1 Operating temperature
Operating temperature should be followed strictly within this specification, especially be careful with maximum temperature.
1) Do not use capacitor above the maximum allowable operating temperature.
2) Surface temperature including self heating should be below maximum operating temperature.
(Due to dielectric loss, capacitor will heat itself when AC is applied. Especially at high frequencies around its SRF, the heat might be so extreme that it may damage itself or the surrounding area.
Please design the circuit so that the maximum temperature of the capacitor including the self heating to be below the maximum allowable operating temperature.
Temperature rise shall be below 20℃)
2-2 Operating voltage
1) Operating voltage across the terminals should be below the rated voltage.
When AC and DC are super imposed, the peak must be below the rated voltage. With AC or pulse overshooting, Vp-p must be below the rated voltage. --------------(1)&(2)
AC or Pulse with overshooting, Vp-p must be below the rated voltage. ----------(3),(4)&(5)
When the voltage is started to apply to the circuit or it is stopped applying, the irregular voltage may be generated for a transit period because of resonance or switching. Be sure to use a
capacitor within rated voltage containing these irregular voltage.
2) Even below the rated voltage, if repetitive high frequency AC or pulse is applied, the reliability of the
capacitor may be reduced.
3) Voltage derating will greatly reduce the failure rate. Since the failure rate follows the 3 power law of
voltage, the failure rate used under Uw with UR rated product will be lowered as (Uw/UR)3 .
No. Process Condition
3 Designing
P.C. board The amount of solder at the terminations has a direct effect on the reliability of the capacitor.
1) The greater the amount of solder, the higher the stress on the chip capacitor, and the more likely that
it will break. When designing a P.C. board, determine the shape and size of the solder pads to have proper amount of solder on the terminations.
2) Avoid using common solder pads for multiple terminations and provide individual solder pads for
each terminations.
See the following table for recommended pad dimensions.
Reflow Soldering
Footprint dimensions in mm
SIZE    A    B    C    D    E    F G
Processing
degraderemarks
Placement
Accuracy 0201 0.65 0.23 0.210.3 N/A0.9 0.6 ± 0.05 0402 1.50 0.50 0.500.500.10  1.750.95± 0.15 0508 2.50 0.50 1.00  2.000.15  2.90  2.40± 0.20 0603 2.30 0.70 0.800.800.20  2.55  1.40± 0.25 0612 2.80 0.80 1.00  3.200.20  3.08  3.85± 0.25 0805 2.80 1.00 0.90  1.300.40  3.05  1.85± 0.25 1206 4.00 2.20 0.90  1.60  1.60  4.25  2.25± 0.25 1210 4.00 2.20 0.90  2.50  1.60  4.25  3.15± 0.25 1808 5.40 3.30 1.05  2.30  2.70  5.80  2.90± 0.25 1812 5.30 3.50 0.90  3.80  3.00  5.55  4.05
Reflow or hot
plate soldering
± 0.25
No. Process Condition
3 Designing
P.C. board
(Continued)
Wave Soldering
Footprint dimensions in mm
SIZE    A    B    C    D    E    F G
Proposed
number &
Dimensions
of dummy tracks
Placement
Accuracy 0603 2.40 1.00 0.700.800.20  3.10  1.901x (0.20x0.80) ± 0.10 0805 3.20 1.40 0.90  1.300.36  4.10  2.501x (0.30x1.30) ± 0.15 1206 4.80 2.30 1.25  1.70  1.25  5.90  3.203x (0.25x1.70) ± 0.25 1210 5.30 2.30 1.50  2.60  1.25  6.30  4.203x (0.25x2.60) ± 0.25 Footprint design for C Array :
Type 0603*4  0402*4
A    2.85 +0.10/-0.05    2.10 ± 0.20
B 0.45 ± 0.05 0.30 ± 0.05
D 0.80 ± 0.10 0.65 ± 0.05
P 0.80 0.50
F    3.10 ± 0.30    1.85 ± 0.25
3) Layout recommendation
Must be
avoided
3 Designing
P.C. board
(Continued)
4) Mechanical stress varies according to location of chip capacitors on the P.C. board.
5) Recommended chip capacitor layout is as follows:
4 Mounting 4-1 Stress from mounting head
If the mounting head is adjusted too low, it may induce excessive stress in the chip capacitor
resulting in cracking. Please take the following precautions.
1) Adjust the bottom dead center of the mounting head to just on the P.C. board surface and not
pressing on it.
2) Adjust the mounting head pressure to be 1 to 3N of static weight.
3) To minimize the impact energy from mounting head, it is important to provide support from the
bottom side of the P.C. board.(see following)
When the centering jaw is worn out, it may give mechanical impact on the capacitor to cause a
crack. Please control the close up dimension of the centering jaw and provide sufficient preventive
maintenance and replacement of it.
4-2 Amount of adhesive
Example : 0805(2012) and 1206(3216)
Figure 0805/1206 case sizes as examples
min
a 0.2mm
b 70 ~ 100 um
c Do not touch the solder land

版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。