专利名称：Flash EEPROM worldline decoder
发明人：Peter W. Lee,Hsing-Ya Tsao,Fu-Chang Hsu 申请号：US08/645630
申请日：19960514
公开号：US05687121A
公开日：
19971111
专利内容由知识产权出版社提供
摘要：A flash memory wordline decoder includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes latches coupled to the wordlines, where the latches are configured to latch the wordlines and to provide an operational voltage on the wordline to accomplish a predetermined operation responsive to the procedure signal. Advantages of the invention include a verification with a low verification voltage such as 1 V or less for operating with a VDD supply voltage as low as 1.5 V. The decoder also reduces erase/write cycle time and improves expected lifetime of the flash memory due to reduced stress on the flash transistors within the flash memory.
decoder申请人：APLUS INTEGRATED CIRCUITS, INC.
代理机构：Flehr Hohbach Test Albritton & Herbert LLP
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