4 Banks x 4M x 4Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of DESCRIPTION
The Hynix HY57V64420HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V64420HG is organized as 4banks of 4,194,304x4.
HY57V644020HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full p
age), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•Single 3.3±0.3V power supply
•All device pins are compatible with LVTTL interface •
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
•
All inputs and outputs referenced to positive edge of system clock
•Data mask function by DQM •
Internal four banks operation
•Auto refresh and self refresh •4096 refresh cycles / 64ms
•
Programmable Burst Length and Burst Type  - 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power Organization Interface Package
HY57V64420HGT-5/55/6/7200/183/166/143MHz
Normal
4Banks x 4Mbits x4LVTTL 400mil 54pin TSOP II
HY57V64420HGT-K 133MHz HY57V64420HGT-H 133MHz HY57V64420HGT-P 100MHz HY57V64420HGT-S 100MHz HY57V64420HGLT-5/55/6/7200/183/166/143MHz
Low power
HY57V64420HGLT-K 133MHz HY57V64420HGLT-H 133MHz HY57V64420HGLT-P 100MHz HY57V64420HGLT-S
100MHz
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock The system clock input. All other inputs are registered  to the SDRAM on the rising edge of CLK
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity
A0 ~ A11Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9 Auto-precharge flag : A10
RAS, CAS, WE Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ3Data Input/Output Multiplexed data input / output pin
V DD/V SS Power Supply/Ground Power supply for internal circuits and input buffers
V DDQ/V SSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 4 I/O Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C )
Note :
1.All voltages are referenced to V SS  = 0V
2.V IH  (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
3.V IL  (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C , V DD =3.3 ± 0.3V, V SS =0V)
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)    For details, refer to AC/DC output circuit
Parameter
Symbol
Rating
Unit
Ambient Temperature T A 0 ~ 70°C Storage Temperature
T STG -55 ~ 125°C Voltage on Any Pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V DD  relative to V SS V DD, V DDQ -1.0 ~ 4.6V Short Circuit Output Current I OS 50mA Power Dissipation
P D 1W Soldering Temperature  ⋅ Time
T SOLDER
260 ⋅ 10
°C  ⋅ Sec
Parameter
Symbol Min Typ.Max Unit Note Power Supply Voltage V DD , V DDQ    3.0  3.3  3.6V 1Input High Voltage V IH    2.0  3.0V DDQ  + 2.0
V 1,2Input Low Voltage
V IL
V SSQ  - 2.0
0.8
V
1,3
Parameter
Symbol Value Unit Note
AC Input High / Low Level Voltage
V IH  / V IL    2.4/0.4V Input Timing Measurement Reference Level Voltage Vtrip    1.4V Input Rise / Fall Time
tR / tF 1ns Output Timing Measurement Reference Level
Voutref    1.4V Output Load Capacitance for Access Time Measurement
CL
50
pF
1
CAPACITANCE (TA=25°C , f=1MHz)
OUTPUT LOAD CIRCUIT
DC CHARACTERISTICS I (TA=0 to 70°C , V DD =3.3±0.3V)
Note :
1.V IN  = 0 to 3.6V, All other pins are not tested under V IN  =0V
2.D OUT  is disabled, V OUT =0 to
3.6V
Parameter
Pin
Symbol Min Max Unit Input capacitance
CLK
C I124pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM
CI 2  2.55pF Data input / output capacitance
DQ0 ~ DQ3
C I/O
2
6.5
pF
decoderParameter
Symbol
Min.Max Unit Note Input Leakage Current I LI -11
uA 1Output Leakage Current I LO -11uA 2
Output High Voltage V OH    2.4-V I OH  = -4mA Output Low Voltage
V OL
-0.4
V
I OL  = +4mA
DC CHARACTERISTICS II (TA=0 to 70°C , V DD =3.3±0.3V, V SS =0V)
Note :
1.I DD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V644020HGT-7/K/H/P/S
4.HY57V644020HGLT-7/K/H/P/S
Parameter
Symbol
Test Condition
Speed
Unit
Note
-6
-7-K -H -P -S Operating Current
I DD1Burst length=1, One bank active t RC  ≥ t RC (min), I OL =0mA 90
85
85
85
80
80
mA 1
Precharge Standby Current in Power Down Mode
I DD2P CKE ≤ V IL (max), t CK  = min 2mA I DD2PS
CKE ≤ V IL (max), t CK  = ∞
2
mA
Precharge Standby Current in Non Power Down Mode
I DD2N
CKE  ≥ V IH (min), CS  ≥ V IH (min), t CK  = min Input signals are changed one time during 2clks. All other pins ≥ V DD -0.2V or ≤ 0.2V 15mA
I DD2NS
CKE  ≥ V IH (min), t CK  = ∞Input signals are stable.12mA Active Standby Current in Power Down Mode
I DD3P CKE ≤ V IL (max), t CK  = min 6mA I DD3PS
CKE ≤ V IL (max), t CK  = ∞
5
mA
Active Standby Current in Non Power Down Mode
I DD3N
CKE  ≥ V IH (min), CS  ≥ V IH (min), t CK  = min Input signals are changed one time during 2clks. All other pins ≥ V DD -0.2V or ≤ 0.2V 30mA
I DD3NS
CKE  ≥ V IH (min), t CK  = ∞Input signals are stable.20
mA Burst Mode Operating Current I DD4t CK  ≥ t CK (min), I OL =0mA All banks active
CL=3150150150
150
120
120
mA 1
CL=2
NA
NA
120
mA Auto Refresh Current I DD5t RRC  ≥ t RRC (min), All banks active 160mA 2Self Refresh Current
I DD6
CKE ≤ 0.2V
1mA 3400
uA
4

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