2012届本科毕业论文
中英文翻译
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完成时间：2012年5月10日
Based on single-chip microcomputer control elevator voice station reporting device
Key words: SCM ISD4004voice station reporting device
1 Introduction
The modern building scale is larger and larger, more and more high on the floor, the elevator technical a
nd quality requirements are also getting higher and higher. Modern elevator technology has been towards faster, more stable, more secure, more humane direction of rapid development.
Elevator voice station reporting device is the embodiment of the humanized design of a specific performance. The elevator will be reported by voice or has reached the floor information, the running state of the elevator, welcome speech and music, can avoid wrong elevator passengers or floor, elimination of people take the elevator to the loneliness.
2 hardware circuit design
The system consists of signal acquisition and isolating circuit, SCM and its peripheral circuit, a speech chip circuit composed of three parts. The elevator floor after signal acquisition isolation after treatment sent to single-chip, single-chip analysis, judgment, extract the effective information, and then by processing output signals to control a speech chip circuit real-time broadcast.
A 2.1 signal acquisition and separation circuit
The newspaper station implement work needs to collect some relevant information to the operation of the elevator, elevator security requires additional system on elevator does not generate interference, the signal acquisition and isolation work is very important.
The system used the elevator control panel on each floor button, elevator
flat-layer signal and switch signal, as shown in table 1:
Table 1the elevator control signal
Considering the signal voltage levels is not a, for the collection of signals required by different treatment. Experiments show that, when the collection circuit input resistance in500K ohm following can result when the signal voltage drop, affect the elevator work; in view of this, the author adopts the high input resistance of the integrated operational amplifier circuit, the corresponding processing as shown in table 2:
Table 2elevator signal processing and Applications
After processing the signal by a photoelectric coupler isolation processing, sent to mcu.
2.2 single chip microcomputer and its peripheral circuit
The system is based on ATMEL 's AT89C51as controller, AT89C51P1.0, P1.1, P1.2, P1.3, P1.4and ISD4004pins respectively1,2,3,28,25 foot link, to control (1,2,3,28,25are respectively the ISD4004chip
select terminal SS, serial input serial output end MOSI, MISO, SCLK, INT serial clock end interrupt ), the remaining pins connected after treatment of floor information: including
1-23floor information signal, DOWN1, UP1peace level DOOR1, DT1, as shown in figure 1
Figure 1 the AT89C51pin wiring diagram
2.3speech chip circuit
Because ISD4004voice chip of the normal working voltage for the 3V, and system using the voltage of 12V, we used the LM317integrated voltage regulator for voltage conversion ( as shown in Figure 2). ISD4004 audio signal output pin AUDOUT pin through a filter capacitor is connected with the loudspeaker, AMCAP automatically mute end, through the use of a capacitor to ground, as shown in figure 3.
ISD4004 series single chip voice recording
The single chip 8to 16 minutes the voice recording
The built-in microcontroller serial communication interface
The 3V single supply
Multi information processing.
The current25-30mA, maintaining the current1 A
The electricity information stored for 100 years ( typical)
The high quality, natural voice restoration technology
The100000 recording cycle ( typical)
Automatic muting function.
The internal adjustment free clock, may choose to use an external clock
ISD4004 series3V working voltage, a recording time of 8to 16 minutes, good sound quality, applicable to mobile phones and other portable electronic products. Chip using CMOS technology, including the oscillator, antialiasing filter, smoothing filter, an audio amplifier, automatic squelch and high-density multi-level flash memory display. Chip design is based on all operations must be controlled by the micr
ocontroller, operation commands through the serial communication interface ( SPI or Microwire ) into. Chip using multilevel direct analog storage technology, each sampled value stored in on-chip flash memory directly, thus can be very real, natural reproduction of voice, music, tone and sound effects, to avoid a general solid recording circuit due to quantization and compression caused by quantization noise and" metallic sound". Sampling frequency for4,5.3,6.4,8.0kHz, the lower the frequency, the longer the sound recording, and decreased, inside information stored in the flash memory in case of a power failure, can be preserved for 100 years
( typical), recording100000 times repeated.
Pin description
Power supply: ( VCCA, VCCD ) to make the noise to a minimum, chip analog and digital circuits using different power supply bus, and are respectively led to the outer package of different pin, analog and digital power supply terminal preferably respectively, walk the line, as far as possible, in close proximity to the power supply terminal is connected, and the decoupling capacitor should be as close to the device.
Ground: ( VSSA, VSSD ) chip internal analog and digital circuits also use different ground.
Noninverting analog input ( IN + ANA ) this is a recording signal in-phase input terminal. Input amplifier available single ended or differential drive. Single end input signal, by a coupling capacitor input maximum amplitude, peak32mV, coupling capacitance and the end of the3K ohm resistive input impedance determines the chip band cutoff frequency. Differential drive signal amplitude, maximum peak to peak value of16mV, ISD33000series of the same.
Reverse analog input ( ANA IN ) differential drive, this is a recording signal to the inverting input. Signal through the coupling capacitor input, maximum amplitude of peak16mV
Audio output ( AUD OUT ) to provide an audio output, can drive5K ohm load. Chip select ( SS ) this end is low, namely to the ISD4004 chip sends instruction, instruction for high level between two.
Serial input ( MOSI ) this end is a serial input end, a main controller in serial the rising edge of the clock before half a cycle of data in the end, for the ISD input.
Serial output ( MISO ) ISD serial output. ISD is not selected, the end is in a high resistance state.
Serial clock ( SCLK ) ISD clock input terminal, by the master controller, MOSI and MISO for synchronous data transmission. Data in SCLK ascending latched onto the ISD, in falling out of the ISD.
Interrupt ( / INT ) the end is an open drain output. ISD in any operationcontroller翻译中文
( including the fast-forward ) was detected in EOM or OVF, the end becomes lower and maintain. Interrupt status in the next SPI cycle begins to clear. Interrupt status is also used RINT instructions read. OVF logo, indicating the ISD book, operation has reached the end of the memory. EOM logo - only in the playback was detected in the internal EOM logo, the status bit is set to 1. Row address clock ( RAC ) open drain outputs. Each of the RAC cycle of said ISD memory operation carried out a row ( in the ISD4004 series
Memory total of 2400 lines ). The signal 175ms to maintain a high level, low level25ms. Fast forward mode, the RAC218.75 s is high,31.25 u s low. The terminal can be used for storage management technology.
External clock ( XCLK ) the end has an internal pull-down element. Chip sampling clock in the factory before calibration, error in the +1%. Commercial grade chip in the temperature and voltage range, frequency variation in
+2.25%. Industrial grade chip in the temperature and voltage range, frequency variation in the - 6 / +4%, then recommend the use of regulated power supply. If greater accuracy is required, from the end
of the external clock input ( as listed in the table ). Due to internal antialiasing smoothing filter is set, so the above recommended clock frequency should not change. Input clock duty cycle be of no great importance, due to internal firstly, frequency divider. In no ground clock, this must end grounding.
Automatic squelch ( AMCAP ) when the recording signal level drops to internally set a threshold, automatically mute function so that the signal is weak, which helps to feed without the noise signal ( mute ). Usually the end of grounding capacitance of 1mF, constitute the internal signal peak value detection circuit part. Detection of the peak level and internal set threshold for comparison, automatic muting function turning point. Large signal, automatic squelch circuit without attenuation, attenuation of6dB mute. The capacitor of the 1mF also affect automatic squelch circuit for signal amplitude response speed. The terminating VCCA disable automatic squelch.

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