© 2001 Fairchild Semiconductor Corporation DS500483
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May 2001Revised May 2001
GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
GTLP10B320
10-Bit LVTTL/GTLP Transceiver
with Split LVTTL Port and Feedback Path
General Description
The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane oper-ation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold le
vels and output edge rate control. The edge rate control minimizes bus settling time.GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.Fairchild’s GTLP has internal edge-rate control and is pro-cess, voltage and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output low level is typ-ically less than 0.5V, the output level high is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic levels s Variable edge rate control pin to select desired edge rate on GTLP port (V ERC )s V REF  pin provides external supply reference voltage for receiver threshold adjustibility s Split LVTTL inputs and outputs
s Special PVT compensation circuitry to provide consis-tent performance over variations of process, supply volt-age and temperature s A feedback path for control and diagnostics monitoring s TTL compatible driver and control inputs
s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedan
ce for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink −24mA/+24mA s B Port sink +50mA
Ordering Code:
Device is also available in Tape and Reel. Specify by appending the suffix letter “X ” to the ordering code.
Order Number Package Number
Package Description
GTLP10B320MTD
MTD56transparent中文意思
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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G T L P 10B 320
Pin Descriptions
Connection Diagram
Functional Description
The GTLP10B320 is a 10-bit Universal driver and receiver containing D-Type flip-flop, latch, and transparent modes of operation for the data paths. In addition there is an internal feedback path that can be used for diagnostic monitoring or caching schemes. Data flow in each direction is controlled by the clock signals (LECLKAB and LECLKBC) and output enables (OEB and OEC). The internal feedback path is controlled by the SEL pin and allows data transfer from Port A to Port C without requiring data to be output to the backplane. The internal feedback path is selected with SEL LOW and the B Port pin is selected with SEL HIGH. The data paths can also be configured for latch/transparent or register mode for each direction with the SAB and SBC
pins. Data polarity is non-inverting with the GTLP outputs enabled via the OEB pin and the LVTTL outputs being enabled via the OEC pin.
For A-to-B data flow the device is configured into a latch/transparent or register mode by pin SAB. If SAB is LOW then the register mode is selected and the device operates on the LOW-to-HIGH transition of LECLKAB. If SAB is HIGH then the latch/transparent configuration is selected and a HIGH-to-LOW transition of LECLKAB stores data in the latch. If LECLKAB is HIGH the device is in transparent mode. When OEB is LOW the outputs are active and when OEB is HIGH the outputs are high impedance.
Pin Names Description
OEB, OEC
B Port,
C Port Output Enable respectively (Active LOW)
V CC , GND, V REF Device Supplies LECLKAB, LECLKBC A-to-B, B-to-C Latch CLK respectively (Transparent Active HIGH)SEL Selects Internal Feedback Path SAB, SBC Selects Register or Latch/Transparent Path for A-to-B and B-to-C respectively B 0-B 9  B Port GTLP I/O A 0-A 9  A Port LVTTL Inputs C 0-C 9  C Port LVTTL Outputs V ERC
Edge Rate Control Pin (GND = Slow Edge Rate)(V CC  = Fast Edge Rate)
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GTLP10B320
Functional Tables
Note 1: Output level before the indicated steady state input conditions were established.Note 2: The data flow of B-to-C is similar except that OEC, SBC and LECLKBC are used.
Note 3: Function identical for SEL = 1 if timing requirements for propagation delay to output and set-up to LECLKBC are met at B Port.Note 4: Output level before the indicated steady state input conditions were established.
I/O Path: SEL = 1 (External Feedback Path) (Note 2)
Inputs
Outputs OEB OEC SAB SBC LECLKAB LECLKBC
Mode (AB)A n C n B n 010X ↑X Register L X L 010X ↑X Register H X H 010X L X Register L X B 0 (Note 1)010X L
X Register H X B 0 (Note 1)
011X ↓X Latch L X L 011X H
X Buffer L X L 011X ↓X Latch H X H 011X H X Buffer H X H 1
1
X
X
X
X
High Impedance
X
X
Z
Internal Feedback Path: SEL = 0 (Internal Feedback Path) (Note 3)
Inputs
Outputs OEB OEC SAB SBC LECLKAB LECLKBC
Mode (AB/BC)A n B n C n 0000↑↑Register/Register L L L 0000↑↑Register/Register H H H 0000L
↑Register/Register X B 0 (Note 4)B 0 (Note 4)
0000↑L Register/Register L L B 0 (Note 4)0000↑L Register/Register H H B 0 (Note 4)
0000L
L
Register/Register X B 0 (Note 4)B 0 (Note 4)
0001↑↓Register/Latch L L L 0001↑H
Register/Buffer L L L 0001↑↓Register/Latch H H H 0001↑H
Register/Buffer H H
H
0001L ↓Register/Latch X B 0 (Note 4)B 0 (Note 4)0001L H Register/Buffer X B 0 (Note 4)B 0 (Note 4)0001L
L
Register/Latch X B 0 (Note 4)B 0 (Note 4)
0010↓↑Latch/Register L L L 0010↓↑Latch/Register H H H 0010↓L Latch/Register L L B 0 (Note 4)0010↓L
Latch/Register H H B 0 (Note 4)
0010H ↑Buffer/Register L L L 0010H ↑Buffer/Register H H H 0010L
L
Latch/Register X B 0 (Note 4)B 0 (Note 4)
0011↓↓Latch/Latch L L L 0011↓↓Latch/Latch H H H 0011H H Buffer/Buffer L L L 0011H H Buffer/Buffer H H H 1
1
X
X
X
X
High Impedance
X
Z
Z
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G T L P 10B 320
Logic Diagram
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GTLP10B320
Absolute Maximum Ratings (Note 5)
Recommended Operating
Conditions
Note 5: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be oper-ated at these limits. The parametric values defined in the “Electrical Char-acteristics ” table are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions ” table will define the conditions for actual device operation.
Note 6: I O  Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V REF  = 1.0V (unless otherwise noted).
Supply Voltage (V CC )−0.5V to +4.6V DC Input Voltage (V I )
−0.5V to +4.6V DC Output Voltage (V O )Outputs 3-STATE −0.5V to +4.6V Outputs Active (Note 6)−0.5V to +4.6V
DC Output Sink Current into C Port I OL
48 mA
DC Output Source Current from C Port I OH
−48 mA
DC Output Sink Current into B Port in the LOW State, I OL 100 mA
DC Input Diode Current (I IK )V I  < 0V
−50 mA DC Output Diode Current (I OK )V O  < 0V −50 mA ESD Rating
>2000V
Storage Temperature (T STG )
−65°C to +150°C
Supply Voltage V CC
3.15V to 3.45V
Bus Termination Voltage (V TT )GTLP    1.47V to 1.53V V REF
0.98V to 1.02V Input Voltage (V I )
on A Port and Control Pins 0.0V to V CC HIGH Level Output Current (I OH )C Port
−24 mA LOW Level Output Current (I OL )C Port +24 mA B Port
+50 mA
Operating Temperature (T A )
−40°C to +85°C
Symbol
Test Conditions
Min Typ Max
Units
(Note 7)
V IH    B Port V REF  + 0.05
V TT
V Others    2.0V IL    B Port 0.0
V REF  − 0.05
V Others 0.8V REF    B Port 0.7  1.0  1.3V V TT    B Port
V REF  + 50 mV
1.5
V CC V V IK V CC  = 3.15V
I I  = −18 mA −1.2
V
V OH
C Port V CC  = Min to Max (Note 8)I OH  = −100 µA V CC  –0.2V
V CC  = 3.15V
I OH  = −8 mA    2.4I OH  = -24mA    2.2
V OL
C Port
V CC  = Min to Max (Note 8)I OL  = 100 µA 0.2V V CC  = 3.15V
I OL  = 8 mA 0.4I OL  = 24 mA 0.5B Port
V CC  = 3.15V I OL  = 40 mA 0.4V I OL  = 50 mA 0.5I I
Control Pins V CC  = 3.45V
V I  = 3.45V 10µA and A Port V I  = 0V −10B Port
V CC  = 3.45V V I  = V TT 5µA V I  = 0
−5I OFF
A or C Ports,V CC  = 0V I  or V O  = 0 to 3.45V
30
µA Control Pins B Port
V CC  = 0V I  or V O  = 0 to 1.5V 30
µA
I I (HOLD)  A Port V CC  = 3.15V V I  = 0.8V 75
µA V I  = 2.0V −75I OZH    C Port V CC  = 3.45V
V O  = 3.45V 10µA B Port V O  = 1.5V 5I OZL    C Port V CC  = 3.45V V O  = 0V −10µA B Port V O  = 0.55V −5I PU/PD
All Ports
V CC  = 0 to 1.5V V I  = 0 to 3.45V
30µA
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G T L P 10B 320
DC Electrical Characteristics  (Continued)
Note 7: All typical values are at V CC  = 3.3V and T A  = 25°C.
Note 8: For conditions shown as Min, use the appropriate value specified under recommended operating conditions.Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than V CC  or GND.
Note: GTLP V REF  and V TT  are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, V TT  and R TERM  can be adjusted beyond the recommended operating to accommodate backplane impedances other than 50Ω, but must remain within the boundaries of the DC Absolute Maximum Ratings. Similarly, V REF  can be adjusted to optimize noise margin.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, V REF  = 1.0V (unless otherwise noted).
Symbol
Test Conditions
Min Typ Max Units
(Note 7)I CC
A or
B Ports V C
C  = 3.45V Outputs HIGH 2745mA or C Port
I O  = 0
Outputs LOW 2745V I  = V CC /V TT  or GND Outputs Disabled 27
45∆I CC    A Port and V CC  = 3.45V,
One Input at V CC 2mA
(Note 9)Control Pins    A or Control Inputs at V CC  or GND −0.6V
C i
Control Pins V I  = V CC  or 0  4.5pF
and A Port C Port V I  = V CC  or 06B Port
V I  = V CC  or 0
9
Symbol
Test Conditions
Min Max
Unit f MAX Maximum Clock Frequency 150MHz t WIDTH Pulse Duration LECLKAB, LECLKBC HIGH or LOW    3.0ns
t SET
Setup Time
SAB = 0  A before LECLKAB ↑  2.1ns
SBC = 0
B before LECLKB
C ↑  2.6SAB = 1, SEL = 1,SBC = 0  A before LECLKBC ↑  6.8SAB = 1, SEL = 0,SBC = 0
A before LECLKBC ↑  3.0SA
B = 1  A before LECLKAB ↓  1.7SB
C = 1
B before LECLKB
C ↓  2.2SAB = 1, SEL = 1,SBC = 1  A before LECLKBC ↓  6.4SAB = 1, SEL = 0,SBC = 1
A before LECLKBC ↓  2.8t HOLD
Hold Time
SAB = 0  A after LECLKAB ↑  2.0ns SBC = 0
B after LECLKB
C ↑  1.6SAB = 1, SEL = 1,SBC = 0  A after LECLKBC ↑−1.4SAB = 1, SEL = 0,SBC = 0
A after LECLKBC ↑  1.4SA
B = 1  A after LECLKAB ↓  2.5SB
C = 1
B after LECLKB
C ↓  2.1SAB = 1, SEL = 1,SBC = 1  A after LECLKBC ↓−1.0SAB = 1, SEL = 0,SBC = 1
A after LECLKBC ↓
1.6

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