Integrated 100G Ethernet Subsystem v2.6 PG165 February 4, 2021Chapter 2:Product Specification
Table 2-14:IEEE 1588 Interface – TX Path
Name I/O Domain Description
CTL_TX_SYSTEMTIMERIN[80-1:0]I TX_CLK System timer input for the TX.
In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds.
In transparent clock mode, bit 63 is the sign bit, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions.
This input must be in the TX clock domain.
TX_PTP_TSTAMP_VALID_OUT O TX_CLK This bit indicates that a valid timestamp is
being presented on the TX.
TX_PTP_PCSLANE_OUT[5-1:0]O TX_CLK This bus identifies which of the 20 PCS lanes that the SOP
was detected on for the corresponding timestamp.
TX_PTP_TSTAMP_TAG_OUT[15:0]O TX_CLK Tag output corresponding to
TX_PTP_TAG_FIELD_IN[15:0].
TX_PTP_TSTAMP_OUT[79:0]O TX_CLK Time stamp for the transmitted packet SOP corresponding to the time at which it passed the capture plane.
The representation of the bits contained in this bus is the same as the timer input.
TX_PTP_1588OP_IN[1:0]I TX_CLK •2’b00 – “No operation”: no timestamp will be taken and the frame will not be modified.
•2’b01 – “1-step”: a timestamp should be taken and inserted into the frame.
•2’b10 – “2-step”: a timestamp should be taken and returned to the client using the additional ports of 2-step operation. The frame itself will not be modified.
•2’b11 – Reserved.
Note:The CMAC core samples this signal at SOP.
Integrated 100G Ethernet Subsystem v2.6 PG165 February 4, 2021Chapter 2:Product Specification
TX_PTP_TSTAMP_OFFSET_IN[15:0]I TX_CLK The usage of this field is dependent on the 1588 operation
•For “No operation” or “2-step” this field will be ignored.
•For “1-step”, this field is a numeric value indicating the number of bytes into the frame to where the first byte of the timestamp to be inserted is located (where a value of 0 represents the first byte of the Destination Address, etc).
This input is also used to specify the offset for the correction field in 1-step Transparent Clock mode.
Note:The IPv6 header size is unbounded, so this field is able to cope with all frames sizes up to 16K jumbo frames.
Note:Only even values are supported.
Note:In transparent clock mode and when
tx_ptp_upd_chksum_in=1, this value cannot be greater than tx_ptp_chksum_offset_in + 34 (decimal).
CTL_TX_PTP_VLANE_ADJUST_MODE I async state When asserted, this signal applies an adjustment to the TX timestamps according to the PCS lane on which the SOP occurs. When zero, no adjustment is made.
transparent中文意思This signal only has effect for 1-step operation.
TX_PTP_RXTSTAMP_IN[63:0]I TX_CLK Reserved
STAT_TX_PTP_FIFO_WRITE_ERROR O TX_CLK Transmit PTP FIFO write error. A 1 on this status indicates that an error occurred during the PTP Tag write. A TX Path reset is required to clear the error.
STAT_TX_PTP_FIFO_READ_ERROR O TX_CLK Transmit PTP FIFO read error. A 1 on this status indicates that an error occurred during the PTP Tag read. A TX Path reset is required to clear the error.
Table 2-14:IEEE 1588 Interface – TX Path (Cont’d)
Name I/O Domain Description
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021Chapter 2:Product Specification RX_LANE_ALIGNER_FILL_7[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane7.RX_LANE_ALIGNER_FILL_8[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane8.RX_LANE_ALIGNER_FILL_9[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane9.RX_LANE_ALIGNER_FILL_10[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane10.RX_LANE_ALIGNER_FILL_11[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane11.RX_LANE_ALIGNER_FILL_12[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane12.RX_LANE_ALIGNER_FILL_13[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane13.RX_LANE_ALIGNER_FILL_14[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane14.RX_LANE_ALIGNER_FILL_15[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane15.RX_LANE_ALIGNER_FILL_16[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane16.RX_LANE_ALIGNER_FILL_17[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane17.RX_LANE_ALIGNER_FILL_18[7-1:0]
O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane18.RX_LANE_ALIGNER_FILL_19[7-1:0]O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane19.Table 2-15:IEEE 1588 Interface – RX Path (Cont’d)
Name
I/O Domain Description Table 2-16:
DRP Path/Control Signals Name I/O
Domain Description DRP_DO[15:0]O
DRP_CLK Data bus for reading configuration data from the 100G Ethernet subsystem to the FPGA logic resources.DRP_RDY O
DRP_CLK Indicates operation is complete for write operations and data is valid for read operations.DRP_ADDR[9:0]I
DRP_CLK DRP address bus.DRP_CLK I
DRP interface clock. When DRP is not used, this can be tied to GND.DRP_DI[15:0]
I DRP_CLK Data bus for writing configuration data from the FPGA logic resources to the 100G Ethernet subsystem.

版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。