Quartus常见错误分析Error
Quartus常见错误分析Error
Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list
----没把singal放到process（）中
2 Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
-=-----可能是说设计中产⽣的触发器没有使能端
3 Error:VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.
------信号类型设置不对，out当作buffer来定义
4 Error:Node instance "clk_gen1" instantiates undefined entity "clk_gen"
-------引⽤的例化元件未定义实体－－entity "clk_gen"
5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated cl ocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer
Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer
6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "datao ut" may not be assigned a new in every possible path through the Process Statement. Signal or variable " dataout" holds its previous in every path with no new assignment, which may create a combinational loo p in the current design.
7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read i nside the Process Statement but isn't in the Process Statement's sensivitity list
-----缺少敏感信号
8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register
9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND
10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.
11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details.
12 Error:VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"
------两者不能连接起来
13 Warning: Ignored node in vector source file. Can't find corresponding node name "clas s_sig[2]" in
design.
------没有编写testbench⽂件，或者没有编辑输⼊变量的值 testbench⾥是元件申明和映射
14 Error:VHDL Binding Indication error at freqdetect_top.vhd(19): port "class"in design entity does
not have std_logic_vector type that is specified for the same generic in the associated com ponent
---在相关的元件⾥没有当前⽂件所定义的类型
15 Error:VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because sign al does not
hold its outside clock edge
16 Warning: Found clock high time violation at 1000.0 ns on register
"|fcounter|lpm_counter:temp_rtl_0|dffs[4]"
17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored ve ctor source file
node.
---"temp[19]"被优化掉了
18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND
19 Warning: Design contains 2 input pin(s) that do not drive logic
Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "sign"
------输出信号与输⼊信号⽆关，
20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"
21 Error:VHDL error at impulcomp.vhd(19): can't implement clock enable condition speci fied using binary
operator "or"
22 Error:VHDL Association List error at period_counter.vhd(38): actual parameter assigne
d to formal
parameter "alarm", but formal parameter is not declared
-------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。
23 Error:Ignored construct behavier at period_counter.vhd(15) because of previous errors －－－－－－－－因为前⼀个错误⽽导致的错误
24 Error:VHDL error at period_counter.vhd(38): type of identifier "alarm" does not agree with its usage
as std_logic type
－－－－－－－－"alarm"的定义类型与使⽤的类型不⼀致
25 Error:VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with condit ions that
test for the edges of multiple clocks
-------同⼀进程中含有两个或多个if(edge)条件，（⼀个进程中之能有⼀个时钟沿）
26 Error:Can't resolve multiple constant drivers for net "datain_reg[22]" at shift_reg.vhd(1 9)
27 can't infer register for signal "num[0]" because signal does not hold its outside clock e dge
28Error: Can't elaborate top-level user hierarchy
register for
29 Error:Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ----------有两
个以上赋值语句，不能确定“cs_in”的值，
30 Warning: Ignored node in vector source file. Can't find corresponding node name "over " in design.
---------------在源⽂件中不到对应的节点“over”。
31 Error:Can't access JTAG chain
⽆法到下载链
32 Info: Assuming node "clk" is an undefined clock
Quartus警告分析Warning
1.Found clock-sensitive change during active clock edge at time
on register ""
原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。⽽时钟敏感信号是不能在时钟边沿变化的。其后果为导致结果不正确。
措施：编辑vector source file
2.Verilog HDL assignment warning at : truncated
with size to match size of target (
原因：在HDL设计中对⽬标的位数进⾏了设定，如:reg[4:0] a;⽽默认为32位,
将位数裁定到合适的⼤⼩
措施：如果结果正确,⽆须加以修正，如果不想看到这个警告，可以改变设定的位数3.All reachable assignments to data_out(10) assign '0', register
removed by optimization
原因：经过综合器优化后，输出端⼝已经不起作⽤了
4.Following 9 pins have nothing, GND, or VCC driving datain port --
changes to this connectivity may change fitting results
原因：第9脚，空或接地或接上了电源
措施：有时候定义了输出端⼝，但输出端直接赋‘0’，便会被接地，赋‘1’接电源。如果你的设计中这些端⼝就是这样⽤的，那便可以不理会这些warning
5.Found pins ing as undefined clocks and/or memory enables
原因：是你作为时钟的PIN没有约束信息。可以对相应的PIN做⼀下设定就⾏了。
主要是指你的某些管脚在电路当中起到了时钟管脚的作⽤，⽐如flip-flop的clk
管脚，⽽此管脚没有时钟约束，因此QuartusII把“clk”作为未定义的时钟。
措施：如果clk不是时钟，可以加“not clock”的约束；如果是，可以在clock setting当中加⼊；在某些对时钟要求不很⾼的情况下，可以忽略此警告或在这
⾥修改:Assignments>Timing >>...
6.Timing characteristics of device EPM570T144C5 are preliminary
原因：因为MAXII 是⽐較新的元件在 QuartusII 中的時序并不是正式版的，要
等 Service Pack
措施：只影响 Quartus 的 Waveform
7.Warning: Clock latency analysis for PLL offsets is supported for the
current device family, but is not enabled
措施：将setting中的timing Requirements&Option-->More Timing
Setting-->setting-->Enable Clock Latency中的on改成OFF
8.Found clock high time violation at 14.8 ns on register
"|counter|lpm_counter:count1_rtl_0|dffs[11]"
原因：违反了steup/hold时间，应该是后仿真，看看波形设置是否和时钟沿符
合steup/hold时间
措施：在中间加个寄存器可能可以解决问题
9.warning: circuit may not operate.detected 46 non-operational
paths clocked by clock clk44 with clock skew larger than data delay
原因：时钟抖动⼤于数据延时，当时钟很快，⽽if等类的层次过多就会出现这种问题，但这个问题多是在器件的最⾼频率中才会出现
措施：setting-->timing Requirements&Options-->Default required
fmax 改⼩⼀些，如改到50MHZ
10.Design contains input pin(s) that do not drive logic
原因：输⼊引脚没有驱动逻辑(驱动其他引脚），所有的输⼊引脚需要有输⼊逻辑措施：如果这种情况是故意的,⽆须理会，如果⾮故意，输⼊逻辑驱动.
11.Warning：Found clock high time violation at 8.9ns on node
'TEST3.CLK'
原因：FF中输⼊的PLS的保持时间过短
措施：在FF中设置较⾼的时钟频率
12.Warning: Found 10 node(s) in clock paths which may be acting as
ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in
clock skew
原因：如果你⽤的 CPLD 只有⼀组全局时钟时，⽤全局时钟分频产⽣的另⼀个时
钟在布线中当作信号处理，不能保证低的时钟歪斜(SKEW)。会造成在这个时钟上⼯作的时序电路不可靠，甚⾄每次布线产⽣的问题都不⼀样。
措施：如果⽤有两组以上全局时钟的 FPGA 芯⽚，可以把第⼆个全局时钟作为另⼀个时钟⽤，可以解决这个问题。
13.Critical Warning: Timing requirements were not met. See Report
window for details.
原因：时序要求未满⾜，
措施：双击Compilation Report-->Time Analyzer-->红⾊部分（如clock setup:'clk'等）-->左键单击list path，查看fmax的SLACK REPORT再根据
提⽰解决，有可能是程序的算法问题
14.Can't achieve minimum setup and hold requirement along
path(s). See Report window for details.
原因：时序分析发现⼀定数量的路径违背了最⼩的建⽴和保持时间，与时钟歪斜有关,⼀般是由于多时钟引起的
措施：利⽤Compilation Report-->Time Analyzer-->红⾊部分（如clock hold:'clk'等），在slack中观察是hold time为负值还是setup time 为负值，然后在：Assignment-->Assignment Editor-->To中增加时钟名(from
node finder)，Assignment Name中增加
和多时钟有关的Multicycle 和Multicycle Hold选项，如hold time为负，可使Multicycle hold的值>multicycle，如设为2和1。
15: Can't analyze file -- file E://quartusii/*/*.v is missing
原因：试图编译⼀个不存在的⽂件，该⽂件可能被改名或者删除了
措施：不管他，没什么影响
16.Warning: Can't find signal in vector source file for input pin
|whole|clk10m
原因：因为你的波形仿真⽂件（ vector source file ）中并没有把所有的输⼊信号(input pin)加进去，对于每⼀个输⼊都需要有激励源的
17.Error: Can't name logic scfifo0 of instance "inst" --
has same name as current design file
原因：模块的名字和project的名字重名了
措施：把两个名字之⼀改⼀下，⼀般改模块的名字
18.Warning: Using design file lpm_fifo0.v, which is not specified as a
design file for the current project, but contains definitions for 1 design
units and 1 entities in project Info: Found entity 1: lpm_fifo0
原因：模块不是在本项⽬⽣成的，⽽是直接copy了别的项⽬的原理图和源程序⽽⽣成的，⽽不是⽤QUARTUS将⽂件添加进本项⽬
措施：⽆须理会，不影响使⽤
19.Timing characteristics of device are preliminary
原因：⽬前版本的QuartusII只对该器件提供初步的时序特征分析
措施：如果坚持⽤⽬前的器件，⽆须理会该警告。关于进⼀步的时序特征分析会在后续版本的Quartus得到完善。
20.Timing Analysis does not support the analysis of latches as
synchronous elements for the currently selected device family
原因：⽤analyze_latches_as_synchronous_elements setting可以让Quaruts II来分析同步锁存，但⽬前的器件不⽀持这个特性
措施：⽆须理会。时序分析可能将锁存器分析成回路。但并不⼀定分析正确。其后果可能会导致显⽰提醒⽤户：改变设计来消除锁存器
21.Warning:Found xx output pins without output pin load capacitance assignment（⽹友：gucheng82提供）
原因：没有给输出管教指定负载电容
措施：该功能⽤于估算TCO和功耗，可以不理会，也可以在Assignment Editor 中为相应的输出管脚指定负载电容，以消除警告
22.Warning: Found 6 node(s) in clock paths which may be acting as
ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in
clock skew
原因：使⽤了⾏波时钟或门控时钟，把触发器的输出当时钟⽤就会报⾏波时钟，将组合逻辑的输出当时钟⽤就会报门控时钟

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