CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.CD40104BMS,CD40194BMS
CMOS 4-Bit Bidirectional Universal Shift Register
Pinouts
CD40104BMS TOP VIEW
CD40194BMS TOP VIEW
Functional Diagrams
CD40104BMS
CD40194BMS
14151691312111012
3457
6
8
OUTPUT ENABLE SHIFT RIGHT IN D0D1D2D3VSS SHIFT LEVEL IN VDD Q1Q2Q3CLOCK SELECT 1SELECT 0
Q01415169131211101
2
3457
6
8
RESET SHIFT RIGHT IN D0D1D2D3VSS SHIFT LEVEL IN VDD Q1Q2Q3CLOCK SELECT 1SELECT 0
Q0345672910
D0D1D2D3
CLOCK
S0
S1
SHIFT LEFT IN SHIFT RIGHT IN
MODE SELECT
1115
14
13
12
Q0Q1Q2Q3
OUTPUT ENABLE 1
VDD = 16VSS = 8
345672910
D0D1D2D3
CLOCK
S0
S1
SHIFT LEFT IN SHIFT RIGHT IN
MODE SELECT
1115
14
13
12
Q0Q1Q2Q3
RESET
1
VDD = 16VSS = 8
Features
•High Voltage Type (20V Rating)
•Medium Speed fCL = 12MHz (typ.) at VDD = 10V •Fully Static Operation
•Synchronous Parallel or Serial Operation •Three State Outputs (CD40104BMS)•Asynchronous Master Reset (CD40194BMS)•5V, 10V and 15V Parametric Ratings
•Standardized Symmetrical Output Characteristics •Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”
Applications
•Arithmetic Unit Bus Registers •Serial/Parallel Conversions
•General Purpose Register for Bus Organized Systems •General Purpose Registers
Description
The CD40104BMS is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a high impedance third output state allowing the device to be used in bus organized systems.
In the parallel load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with serial data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the register is accomplished by setting both mode controls low and clocking the register. When the output enable input is low, all outputs assume the high impedance state.
The CD40194BMS is a universal shift register featuring parallel inputs,parallel outputs SHIFT RIGHT
and SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the out-put after the positive transition of the CLOCK input. During loading,serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of the register is inhibited when both mode control inputs are low. When low, the RESET input resets all stages and forces all outputs low. The CD40194BMS is similar to industry types 340194 and MC40194.The CD40104BMS and CD40194BMS series types are supplied in these 16 lead outline packages
Braze Seal DIP *HNX,†H4W Frit Seal DIP *H1L,†HIF
Ceramic Flatpack
H6W
*CD40104B Only
†CD40194B Only
File Number
3352
December 1992
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . .-0.5V to +20V (Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range. . . . . . . . . . . . . . . .-55o C to +125o C Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . .-65o C to +150o C Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . .+265o C At Distance 1/16 ± 1/32 Inch (1.59mm± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . .θjaθjc Ceramic DIP and FRIT Package. . . . .80o C/W20o C/W Flatpack Package . . . . . . . . . . . . . . . .70o C/W20o C/W Maximum Package Power Dissipation (PD) at +125o C
For T A = -55o C to +100o C (Package Type D, F, K) . . . . . .500mW For T A = +100o C to +125o C (
Package Type D, F, K). . . . . .Derate
Linearity at 12mW/o C to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . .100mW For T A = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175o C
TABLE1.DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS(NOTE 1)
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITS
MIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND1+25o C-10µA
2+125o C-1000µA
VDD = 18V, VIN = VDD or GND3-55o C-10µA Input Leakage Current IIL VIN = VDD or GND VDD = 20V1+25o C-100-nA
2+125o C-1000-nA
VDD = 18V3-55o C-100-nA Input Leakage Current IIH VIN = VDD or GND VDD = 20V1+25o C-100nA
2+125o C-1000nA
VDD = 18V3-55o C-100nA Output Voltage VOL15VDD = 15V, No Load1, 2, 3+25o C, +125o C, -55o C-50mV Output Voltage VOH15VDD = 15V, No Load (Note 3)1, 2, 3+25o C, +125o C, -55o C14.95-V Output Current (Sink)IOL5VDD = 5V, VOUT = 0.4V1+25o C0.53-mA Output Current (Sink)IOL10VDD = 10V, VOUT = 0.5V1+25o C  1.4-mA Output Current (Sink)IOL15VDD = 15V, VOUT = 1.5V1+25o C  3.5-mA Output Current (Source)IOH5A VDD = 5V, VOUT = 4.6V1+25o C--0.53mA Output Current (Source)IOH5B VDD = 5V, VOUT = 2.5V1+25o C--1.8mA Output Current (Source)IOH10VDD = 10V, VOUT = 9.5V1+25o C--1.4mA Output Current (Source)IOH15VDD = 15V,
VOUT = 13.5V1+25o C--3.5mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA1+25o C-2.8-0.7V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA1+25o C0.7  2.8V
Functional F VDD = 2.8V, VIN = VDD or GND7+25o C VOH >
VDD/2VOL <
VDD/2
V
VDD = 20V, VIN = VDD or GND7+25o C
VDD = 18V, VIN = VDD or GND8A+125o C
VDD = 3V, VIN = VDD or GND8B-55o C
Input Voltage Low
(Note 2)
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V1, 2, 3+25o C, +125o C, -55o C-  1.5V
Input Voltage High
(Note 2)
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V1, 2, 3+25o C, +125o C, -55o C  3.5-V
Input Voltage Low (Note 2)VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3+25o C, +125o C, -55o C-4V
Input Voltage High (Note 2)VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3+25o C, +125o C, -55o C11-V
Tri-State Output Leakage IOZL VIN = VDD or GND
VOUT = 0V
VDD = 20V1+25o C-0.4-µA
2+125o C-12-µA
VDD = 18V3 -55o C-0.4-µA
Tri-State Output Leakage IOZH VIN = VDD or GND
VOUT = VDD
VDD = 20V1+25o C-0.4µA
2+125o C-12µA
VDD = 18V3 -55o C-0.4µA
NOTES:  1.All voltages referenced to device GND, 100% testing being implemented.
2.Go/No Go test with limits applied to inputs.
3.For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
TABLE2.AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITS
MIN MAX
Propagation Delay Clock to Q TPHL
TPLH
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
9+25o C-440ns
10, 11+125o C, -55o C-594ns
Propagation Delay
CD40194BMS Reset to Q TPHL VDD = 5V, VIN = VDD or GND
(Note 1, 2)
9+25o C-460ns
10, 11+125o C, -55o C-621ns
Propagation Delay CD40104BMS 3-State TPZH
TPZL
TPLZ
VDD = 5V, VIN = VDD or GND
(Note 2, 3)
9+25o C-160ns
10, 11+125o C, -55o C-216ns
Propagation Delay CD40104BMS 3-State TPHZ VDD = 5V, VIN = VDD or GND
(Note 2, 3)
9+25o C-90ns
10, 11+125o C, -55o C-122ns
Transition Time TTHL
TTLH VDD = 5V, VIN = VDD or GND
(Note 1, 2)
9+25o C-200ns
10, 11+125o C, -55o C-270ns
Maximum Clock Input Frequency FCL VDD = 5V, VIN = VDD or GND
(Note 1, 2)
9+25o C3-MHz
10, 11+125o C, -55o C  2.22-MHz
NOTES:
1.CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2.-55o C and +125o C limits guaranteed, 100% testing being implemented.
3.VDD = 5V, CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE3.ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITS MIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND1, 2-55o C, +25o C-5µA
+125o C-150µA
VDD = 10V, VIN = VDD or GND1, 2-55o C, +25o C-10µA
+125o C-300µA
VDD = 15V, VIN = VDD or GND1, 2-55o C, +25o C-10µA
+125o C-600µA Output Voltage VOL VDD = 5V, No Load1, 2+25o C, +125o C,
-55o C
-50mV
Output Voltage VOL VDD = 10V, No Load1, 2+25o C, +125o C,
-55o C
-50mV
Output Voltage VOH VDD = 5V, No Load1, 2+25o C, +125o C,
-55o C
4.95-V
Output Voltage VOH VDD = 10V, No Load1, 2+25o C, +125o C,
-55o C
9.95-V Output Current (Sink)IOL5VDD = 5V, VOUT = 0.4V1, 2+125o C0.36-mA
-55o C0.64-mA Output Current (Sink)IOL10VDD = 10V, VOUT = 0.5V1, 2+125o C0.9-mA
-55o C  1.6-mA Output Current (Sink)IOL15VDD = 15V, VOUT = 1.5V1, 2+125o C  2.4-mA
-
55o C  4.2-mA Output Current (Source)IOH5A VDD = 5V, VOUT = 4.6V1, 2+125o C--0.36mA
-55o C--0.64mA
Output Current (Source)IOH5B VDD = 5V, VOUT = 2.5V1, 2+125o C--1.15mA
-55o C--2.0mA Output Current (Source)IOH10VDD = 10V, VOUT = 9.5V1, 2+125o C--0.9mA
-55o C--1.6mA Output Current (Source)IOH15VDD =15V, VOUT = 13.5V1, 2+125o C--2.4mA
-55o C--4.2mA
Input Voltage Low VIL VDD = 10V, VOH > 9V,
VOL < 1V 1, 2+25o C, +125o C,
-55o C
-3V
Input Voltage High VIH VDD = 10V, VOH > 9V,
VOL < 1V 1, 2+25o C, +125o C,
-55o C
7-V
Propagation Delay Clock to Q TPHL
TPLH
VDD = 10V1, 2, 3+25o C-200ns VDD = 15V1, 2, 3+25o C-140ns
Propagation Delay CD40194B Reset to Q TPLH
TPHL
VDD = 10V1, 2, 3+25o C-180ns VDD = 15V1, 2, 3+25o C-130ns
Propagation Delay CD40104BMS 3-State TPZH
TPZL
TPLZ
VDD = 10V1, 2, 3, 4+25o C-70ns VDD = 15V1, 2, 3, 4+25o C-50ns
Propagation Delay CD40104BMS 3-State TPHZ VDD = 10V1, 2, 4+25o C-50ns VDD = 15V1, 2, 4+25o C-40ns
Transition Time TTHL
TTLH VDD = 10V1, 2, 3+25o C-100ns VDD = 15V1, 2, 3+25o C-80ns
Minimum Data Setup Time, D0, D3, SRIN, SLIN to Clock TS VDD = 5V1, 2, 3+25o C-100ns VDD = 10V1, 2, 3+25o C-70ns VDD = 15V1, 2, 3+25o C-50ns
Minimum Data Hold Time D0, D3, SRIN, SLIN to Clock TH VDD = 5V1, 2, 3+25o C-0ns VDD = 10V1, 2, 3+25o C-0ns VDD = 15V1, 2, 3+25o C-0ns
Minimum Clock Pulse Width TW VDD = 5V1, 2, 3+25o C-180ns VDD = 10V1, 2, 3+25o C-80ns VDD = 15V1, 2, 3+25o C-50ns
Maximum Clock Rise and Fall Time TRCL
TFCL
VDD = 5V1, 2, 3, 5+25o C3-µs VDD = 10V1, 2, 3, 5+25o C6-µs VDD = 15V1, 2, 3, 5+25o C8-µs
Minimum Data Setup Time
Select 1, Select 0 to Clock TS VDD = 5V1, 2, 3+25o C-400ns VDD = 10V1, 2, 3+25o C-220ns VDD = 15V1, 2, 3+25o C-130ns
Minimum Data Hold Time Select 1, Select 0 to Clock TH VDD = 5V1, 2, 3+25o C-0ns VDD = 10V1, 2, 3+25o C-0ns VDD = 15V1, 2, 3+25o C-0ns
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE UNITS
MIN MAX
Minimum Reset Pulse Width CD40194BMS
TW
VDD = 5V 1, 2, 3+25o C -300ns VDD = 10V 1, 2, 3+25o C -200ns VDD = 15V
1, 2, 3+25o C -140ns Input Capacitance CIN
Any Input
1, 2
+25o C
-7.5
pF
NOTES:
1.All voltages referenced to device GND.
2.The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.
3.CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4.CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5.If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
TABLE 4.POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS
NOTES TEMPERATURE
LIMITS
UNITS MIN MAX Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4+25o C -25µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4+25o C -2.8-0.2V N Threshold Voltage Delta
∆VTN VDD = 10V, ISS = -10µA 1, 4+25o C -±1V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4+25o C 0.2  2.8V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA
1, 4+25o C -±1V Functional
F
VDD = 18V, VIN = VDD or GND 1
+25o C
VOH >VDD/2VOL <VDD/2V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL TPLH
VDD = 5V
1, 2, 3, 4
+25o C
-  1.35 x +25o C Limit
ns
NOTES:  1.All voltages referenced to device GND.
2.CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3.See Table 2 for +25o C limit.
4.Read and Record
TABLE 5.BURN-IN AND LIFE TEST DELTA PARAMETERS +25o C PARAMETER
SYMBOL DELTA LIMIT
Supply Current - MSI-2IDD ± 1.0µA
Output Current (Sink)IOL5± 20% x Pre-Test Reading Output Current (Source)
register for
IOH5A
± 20% x Pre-Test Reading
PARAMETER SYMBOL CONDITIONS
NOTES TEMPERATURE
UNITS MIN MAX

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