MC14094B
8-Stage Shift/Store Register with Three-State Outputs
The MC14094B combines an 8–stage shift register with a data latch for each stage and a three–state output from each latch.
Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The Q S  output data is for use in high–speed cascaded systems. The Q ′S  output data is shifted on the following negative clock transition for use in low–speed cascaded systems.
Data from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high.
Outputs of the eight data latches are controlled by three–state buffers which are placed in the high–impedance state by a logic Low on Output Enable.
•Three–State Outputs
•Capable of Driving Two Low–Power TTL Loads or One Low–Power Schottky TTL Load Over the Rated Temperature Range •Input Diode Protection •Data Latch
•Dual Outputs for Data Out on Both Positive and Negative Clock Transitions
•Useful for Serial–to–Parallel Data Conversion •
Pin–for–Pin Compatible with CD4094B
MAXIMUM RATINGS (Voltages Referenced to V
) (Note 2.)
may occur.
3.Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V in  and V out  should be constrained to the range V SS  v  (V in  or V out ) v  V DD .
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS  or V DD ). Unused outputs must be left open.
Device Package Shipping ORDERING INFORMATION
MC14094BCP PDIP–162000/Box MC14094BD SOIC–16onsemi
48/Rail MC14094BDR2SOIC–162500/T ape & Reelregister for
MC14094BDT TSSOP–1696/Rail MC14094BDTR2TSSOP–162500/T ape & Reel MARKING DIAGRAMS
116
PDIP–16P SUFFIX CASE 648
MC14094BCP AWLYYWW SOIC–16D SUFFIX CASE 751B
TSSOP–16DT SUFFIX CASE 948F
116
14094B AWLYWW
14094B ALYW 116
A = Assembly Location WL, L = Wafer Lot YY , Y = Year
WW, W
= Work Week
SOEIAJ–16F SUFFIX CASE 966
1
16
MC14094B ALYW MC14094BF
SOEIAJ–16
See Note 1.
1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
Q7Q6Q5OUTPUT ENABLE V DD
Q S
Q ′S Q8Q1CLOCK
DATA STROBE V SS
Q4Q3Q2PIN ASSIGNMENT
* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q S .
5.The formulas given are for the typical characteristics only at 25_C.
6.To calculate total supply current at loads other than 50 pF:
I T(C L) = I T(50 pF) + (C L – 50) Vfk
where: I T is in µA (per package), C L in pF, V = (V DD – V SS) in volts, f in kHz is input frequency, and k = 0.001.
7.The formulas given are for the typical characteristics only at 25_C.
8.Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3–STATE TEST CIRCUIT
AND t PZL OUTPUT
O.E.CLOCK
ST DATA
BLOCK DIAGRAM
15
4
567141312
1110
9
Q1
Q2Q ′S
Q3Q4Q5Q6Q7
Q8
Q S

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