READ LOCK REGISTER
The device is first selected by driving chip select (S#) LOW. The command code for the
READ LOCK REGISTER command is followed by a 3-byte address (A23-A0) pointing to
any location inside the concerned sector (or subsector). Each address bit is latched-in
during the rising edge of serial clock (C). Then the value of the lock register is shifted
out on serial data output (DQ1), each bit being shifted out at a maximum frequency f C during the falling edge of C.
The READ LOCK REGISTER command is terminated by driving S# HIGH at any time
during data output.
Figure 17: READ LOCK REGISTER Command Sequence
DQ[0]
C
DQ1
Don’t Care
Any READ LOCK REGISTER command issued while an ERASE, PROGRAM, or WRITE
cycle is in progress is rejected without any effect on the cycle that is in progress.
Values of b1 and b0 after power-up are defined in the table below.
Table 14: Lock Register Out
PAGE ERASE
The PAGE ERASE command sets to 1 (FFh) all bits inside the chosen page. Before the
PAGE ERASE command can be accepted, a WRITE ENABLE command must have been
executed previously. After the WRITE ENABLE command has been decoded, the device
sets the write enable latch (WEL) bit.
The PAGE ERASE command is entered by driving chip select (S#) LOW, followed by the
command code, and three address bytes on serial data input (DQ0). Any address inside
the sector is a valid address for the PAGE ERASE command. S# must be driven LOW for
the entire duration of the sequence.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in.
Otherwise the PAGE ERASE command is not executed. As soon as S# is driven HIGH,
the self-timed PAGE ERASE cycle is initiated; the cycle's duration is t PE. While the PAGE
ERASE cycle is in progress, the status register may be read to check the value of the write
in progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE ERASE cycle, and is 0
when the cycle is completed. At some unspecified time before the cycle is completed,
the WEL bit is reset.
A PAGE ERASE command applied to a page that is hardware or software protected is not
executed.
A PAGE ERASE command while an ERASE, PROGRAM, or WRITE cycle is in progress is
rejected without having any effects on the cycle that is in progress.
If RESET# is driven LOW while a PAGE ERASE cycle is in progress, the PAGE ERASE cycle
is interrupted and the programmed data may be corrupted. On RESET going LOW, the
device enters the reset mode and a time of t RHSL is then required before the device can
be reselected by driving Chip Select (S#) LOW.
Figure 21: PAGE ERASE Command Sequence
C
register for
DQ0
Notes:  1.Address bits A23-A18 are don't care in the M25PE20. Address bits A23-A17 are don't
care in the M25PE10.
2.Address bits A23-A19 are don't care.
3.Address bits A23-A20 are don't care.
SUBSECTOR ERASE
The SUBSECTOR ERASE command sets to 1 (FFh) all bits inside the chosen subsector.Before the SUBSECTOR ERASE command can be accepted, a WRITE ENABLE com-mand must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit.
The SUBSECTOR ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address inside the subsector is a valid address for the SUBSECTOR ERASE command. S# must be driven LOW for the entire duration of the sequence.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in.Otherwise the SUBSECTOR ERASE command is not executed. As soon as S# is driven HIGH, the self-timed SUBSECTOR ERASE cycle is initiated; the cycle's duration is t SSE .While the SUBSECTOR ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SUBSECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is complete, the WEL bit is reset.
A SUBSECTOR ERASE command issued to a sector that is hardware or software protec-ted is not executed.
Any SUBSECTOR ERASE command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress.
If RESET# is driven LOW while a SUBSECTOR ERASE cycle is in progress, the SUBSEC-TOR ERASE cycle is interrupted and data may not be erased correctly. On RESET# going LOW, the device enters the RESET mode and a time of t RHSL  is then required before the device can be reselected by driving S# LOW.
Figure 22: SUBSECTOR ERASE Command Sequence
DQ0
C
S#
2134567892930310
Notes:  1.Address bits A23-A18 are don't care  in the M25PE20. Address bits A23-A17 are don't
care  in the M25PE10.
2.Address bits A23-A19 are don't care .
3.Address bits A23-A20 are don't care .
SECTOR ERASE
The SECTOR ERASE command sets to 1 (FFh) all bits inside the chosen sector. Before the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit.
The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address in-side the sector is a valid address for the SECTOR ERASE command. S# must be driven LOW for the entire duration of the sequence.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in.Otherwise the SECTOR ERASE command is not executed. As soon as S# is driven HIGH,the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is t SE . While the SECTOR ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is completed, the WEL bit is reset.
A SECTOR ERASE command applied to a sector that contains a page that is hardware protected is not executed.
Any SECTOR ERASE command while an ERASE, PROGRAM, or WRITE cycle is in pro-gress is rejected without having any effects on the cycle that is in progress.
If RESET# is driven LOW while a SECTOR ERASE cycle is in progress, the SECTOR
ERASE cycle is interrupted and the programmed data may be corrupted. On RESET go-ing LOW, the device enters the reset mode and a time of t RHSL  is then required before the device can be reselected by driving Chip Select (S#) LOW.
Figure 23: SECTOR ERASE Command Sequence
C
DQ0S#
2134567892930310
Notes:  1.Address bits A23-A18 are don't care  in the M25PE20. Address bits A23-A17 are don't
care  in the M25PE10.
2.Address bits A23-A19 are don't care  .
3.Address bits A23-A20 are don't care  .

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