专利名称：Semiconductor memory device with common
I/O type circuit configuration achieving write
before sense operation
发明人：Takayuki Gyohten,Masaru Haraguchi,Fukashi
Morishita
申请号：US10671795
申请日：20030929
公开号：US07064993B2
公开日：
20060620
专利内容由知识产权出版社提供
专利附图：
摘要：A connection gate circuit includes first and second N channel MOS transistors
connected in series between a first bit line of a pair of bit lines and a first global IO line of a pair of IO lines, and third and fourth N channel MOS transistors connected in series between a second bit line of the pair of bit lines and a second global IO line of the pair of IO lines. The first and second N channel MOS transistors have their gates receiving a sense amplifier activation signal activating a sense amplifier. The third and fourth N channel MOS transistors have their gates receiving a column selection signal.
申请人：Takayuki Gyohten,Masaru Haraguchi,Fukashi Morishita
地址：Hyogo JP,Hyogo JP,Hyogo JP
国籍：JP,JP,JP
代理机构：McDermott Will & Emery LLP
typec数据线
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