R SENSE LOGIC
OUT V
V DS - Drain-to-Source Voltage - V
I D -D r a i n -t o -S o u r c e C u r r e n t -A
DRAIN-TO-SOURCE CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
TPS2492TPS2493
www.ti
SLUSA65B –JULY 2010–REVISED OCTOBER 2011
Positive High-Voltage Power-Limiting Hotswap Controller
With Analog Current Monitor Output
Check for Samples:TPS2492,TPS2493
FEATURES
DESCRIPTION
•9-V to 80-V Operation
The TPS2492and TPS2493are easy-to-use,positive •High-Side Drive for External N-FET high voltage,14-pin Hotswap Controllers that safely •Programmable FET Power Limit drive an external N-channel FET to control load current.The programmable power foldback protection •Programmable Load Current Limit ensures that the external FET operates inside its safe •Programmable Fault Timer operating area (SOA)during overload conditions by •Load Current Monitor Output controlling of power dissipation.The programmable current limit and fault timer ensure the supply,•Power Good and Fault Outputs external FET,and load are not harmed by •Enable/UV,OV Inputs
overcurrent.Features include inrush current limiting,•Latch or Auto Restart After Fault controlled load turn-on,interfacing to down-stream •EVM Available SLUU425
DC-to-DC converters,and power feed protection.•
Calculation Tool Available SLVC033
The analog current monitor output provides a signal ready for sampling with an external A/D converter.APPLICATIONS
Additional features include programmable overvoltage •Server Backplanes
and undervoltage shutdown,power-good for coordinating loads with inrush,and a fault indicator to •Storage Area Networks (SAN)indicate an over-current shutdown.
•Medical Systems •Plug-in Modules •
Base Stations
Typical Application Circuit
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.Copyright ©2010–2011,Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
TPS2492
TPS2493
SLUSA65B–JULY2010–REVISED OCTOBER2011www.ti
PRODUCT INFORMATION(1)
TEMPERATURE FUNCTION PACKAGE PART NUMBER
Latched TPS2492PW -40°C to125°C PW14
timeout on t2 timerRetry TPS2493PW
(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or visit the
device product folder on www.ti.
ABSOLUTE MAXIMUM RATINGS(1)
over recommended T J and voltages with respect to GND(unless otherwise noted)
VALUE UNIT
VCC,SENSE,UVEN,OUT-0.3to100
Input voltage range
PROG,OV-0.3to6
VCC–SENSE Differential voltage-1.5to1.5V GATE,PG,FLT-0.3to100
Output voltage range
TIMER,VREF,IMON-0.3to6
PG,FLT10
Sink current
PROG2mA VREF Source current2
HBM2
ESD rating kV
CDM0.5
(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings
only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC(1)VALUE UNITS
θJA Junction-to-ambient thermal resistance(2)116.4
θJB Junction-to-board thermal resistance(3)53.8
°C/W
ψJT Junction-to-top characterization parameter(4)  1.4
ψJB Junction-to-board characterization parameter(5)58.8
(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.
(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as
specified in JESD51-7,in an environment described in JESD51-2a.
(3)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature,as described in JESD51-8.
(4)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).
(5)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).
RECOMMENDED OPERATING CONDITIONS
over recommended T J and voltages with respect to GND(unless otherwise noted)
MIN NOM MAX UNIT
VCC980 Input voltage range V PROG0.44 Sourcing current01mA VREF
capacitive loading01000pF
IMON Sourcing current  1.9mA
T J Junction operating temperature-40125°C
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TPS2492
TPS2493 www.ti SLUSA65B–JULY2010–REVISED OCTOBER2011 ELECTRICAL CHARACTERISTICS
9V≤V VCC≤80V,-40°C≤T J≤125°C,V TIMER=0V and all outputs unloaded.Typical specification are at T J=25°C,V VCC= 48V(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Current(VCC)
I VCC Enabled V UVEN=Hi,V SENSE=V OUT=V VCC6651000
µA
I VCC Disabled V UVEN=Lo,V SENSE=V VCC,V OUT=0120250
Input Supply UVLO(VCC)
V VCC turn on Rising8.48.8V
Hysteresis50100150mV
Current Sense Input(SENSE)
I SENSE Input bias current V SENSE=V OUT=V VCC7.520µA
Reference Voltage Output(VREF)
V REF Reference voltage0≤I VREF≤1mA  3.94  4.1V
Power Limiting Input(PROG)
Input bias current;device
I PROG0.4≤V PROG≤4V V UVEN=48V5µA
enabled;sourcing or sinking
Pull down resistance;device
R PROG I PROG=200µA;V UVEN=0V375600Ωdisabled
Power Limiting and Current Limiting(SENSE)
Current limit threshold V PROG=2.4V;V OUT=0V;V VCC=48V172533
V(VCC-SENSE)with power limiting
V PROG=0.9V;V OUT=30V;V VCC=48V172533 trip
mV Current limit threshold
V(VCC-SENSE)without power V PROG=4V;V SENSE=V OUT455055
limiting trip
V PROG=4V;V OUT=V SENSE;V(VCC-SENSE):0
Large overload response time to
t F_TRIP rising to200mV;C(GATE-OUT)=2nF;  1.2µs GATE low
V(GATE-OUT)=1V
TIMER Operation(TIMER)
V TIMER=0V172736
I SOURCE TIMER source current
V TIMER=0V;T J=25°C222732
µA
V TIMER=5V  1.5  2.7  3.7
I SINK TIMER sink current
V TIMER=5V;T J=25°C  2.1  2.7  3.1
TIMER upper threshold  3.940  4.1
V TIMER V TIMER lower reset threshold TPS2492only0.96  1.00  1.04
D RETRY Fault retry duty cycle TPS2493only0.50.751%
Fault Indicator Output(FLT)
I FLT=2mA0.10.25
Low voltage(sinking)V
I FLT=4mA0.250.5
I LEAKAGE Leakage current FLT high impedance10µA
Under-Voltage and Enable Input(UVEN)
V UVEN_H UVEN rising  1.31  1.35  1.39V Threshold voltage
Hysteresis80100120mV
Leakage current V UVEN=48V1µA Copyright©2010–2011,Texas Instruments Incorporated Submit Documentation Feedback3
TPS2492
TPS2493
SLUSA65B–JULY2010–REVISED OCTOBER2011www.ti ELECTRICAL CHARACTERISTICS(continued)
9V≤V VCC≤80V,-40°C≤T J≤125°C,V TIMER=0V and all outputs unloaded.Typical specification are at T J=25°C,V VCC= 48V(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Gate Drive Output(GATE)
GATE sourcing current V SENSE=V VCC;V(GATE-OUT)=7V;V UVEN=Hi152235µA
V UVEN=Lo;V GATE=V VCC  1.8  2.4  2.8
I GATE
GATE sinking current mA
V UVEN=Hi;V GATE=V VCC;V VCC-V SENSE=
75125250
200mV
V UVEN=Hi,VCC=SENSE=OUT,measure
V GATE GATE output1216V
V GATE-V OUT
Propagation delay:UVEN going V UVEN=0→2.5V,50%of V UVEN to50%of
t D_ON2540 high to GATE output high V GATE,V OUT=V VCC,R(GATE-OUT)=1MΩ
V UVEN=2.5V→0V,50%of V UVEN to50%
Propagation delay:UVEN going
t D_OFF of V GATE,V OUT=V VCC,R(GATE-OUT)=1MΩ,0.51 low to GATE output lowµs
t FALL<0.1µs
V TIMER:0→5V,t RISE<0.1µs.50%of
Propagation delay:TIMER expires
t D_FAULT V TIMER to50%of V GATE,V OUT=VCC,0.81 to GATE output low
R(GATE-OUT)=1MΩ,
Power Good Output(PG)
I PG=2mA0.10.25
Low voltage(sinking)
I PG=4mA0.250.5
PG threshold voltage;V OUT rising;
V SENSE=V VCC;measure V(VCC-OUT)0.8  1.25  1.7 PG goes low
V PG threshold voltage;V OUT
V SENSE=V VCC;measure V(VCC-OUT)  2.2  2.7  3.2 falling;PG goes open drain
PG threshold hysteresis voltage;
V SENSE=V VCC  1.4
V(SENSE-OUT)
PG deglitch delay;detection to
t DPG V SENSE=V VCC5915ms output;rising and falling edges
I LEAKAGE Leakage current;PG false open drain10µA
Overvoltage Input(OV)
V OV_H OV rising  1.31  1.35  1.39V Threshold voltage
Hysteresis7090110mV
I LEAKAGE Leakage current(sinking)V OV=5V1µA
t OFF Turn off time V OV=0→2.5V to V GS<1V,C GATE=2nF2
µs Maximum duration of OV strong
Gate pull down40100220 pull down
Output Voltage Feedback(OUT)
V OUT=V VCC,V UVEN=Hi;sinking820
I OUT Bias currentµA
V OUT=GND;V UVEN=Lo;sourcing1840
Load Current Monitor(IMON)Output
Maximum output voltage V CC–V SENSE=200mV  2.6  2.83V
I SOURCE Source current  1.9mA
I SINK Sink current60µA
Gain(V IMON/V(VCC-SENSE))464850V/V
V OFFSET Offset voltage-50-530mV
Error relative to curve fit,5mV<(V CC–
Linearity(1)0.3%
V SENSE)
Output Ripple(1)8mV PP (1)These parameters are provided for reference only,and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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TIMER
FLT
PG
IMON
OUT
GATE VREF
VCC PROG SENSE GND UVEN OV TPS2492TPS2493
www.ti
SLUSA65B –JULY 2010–REVISED OCTOBER 2011
DEVICE INFORMATION
Functional Block Diagram
Copyright ©2010–2011,Texas Instruments Incorporated Submit Documentation Feedback 5

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