NTE2732A
Integrated Circuit
32K (4K x 8) NMOS UV Erasable PROM
Description:
The NTE2732A is a 32,768–bits ultraviolet erasable and electrically programmable read–only memory (EPROM) organized as 4,096 words by 8 bits and manufactured using N–Channel Si–Gate MOS processing.  With its single +5V power supply and with an access time of 200ns, the NTE2732A is ideal for use with high performance +5V microprocessors such as the NTE3880.
The NTE2732A has an important feature which is the separate output control, Output Enable (OE) from the Chip Enable control (CE).  The OE control eliminates bus contention in multiple bus micropro-cessor systems.
The NTE2732A also features an standby mode which reduces the power dissipation without increas-ing access time.  The active current is 125mA while the maximum standby mode is achieved by apply-ing a TTL–high signal to the CE input.
Features:
D Fast Access Time:  200ns Max
D0° to +70°C Standard Temperature Range
D Single +5V Power Supply
D Low Standby Current (35mA Max)
D Inputs and Outputs TTL Compatible During Read and Program
D Completely Static
Absolute Maximum Ratings:  (Note 1)
All Input or Output Voltages with respect to GND, V I+6 to –0.6V
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Supply Voltage with respect to GND during Program, V pp+22 to –0.6V
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Ambient Temperature under Bias, T A –10° to +80°C
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Storage Temperature Range, T stg –65° to +125°C Note  1.Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.  This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi-cation is not implied.  Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Modes:
Read Operation (DC and AC Conditions):
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Operating Temperature Range, T opr0° to +70°C
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V CC Power Supply (Note 2, Note 3) 5V ± 5% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V pp Voltage (Note 3) V pp = V CC Note  2.V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. Note  3.V PP may be connected directly to V CC except during programming.  The supply current would then be the sum of I CC and I PP1.
DC and Operating Characteristics:
Note  3.V PP may be connected directly to V CC except during programming.  The supply current would then be the sum of I CC and I PP1.
Note  4.Typical values are for T A = +25°C and nominal supply voltages.
AC Characteristics:
Note  4.Typical values are for T A = +25°C and nominal supply voltages.
Note  5.This parameter is only sampled and is not 100% tested.
Capacitance:(T = +25°C, f = 1MHz, Note 5 unless otherwise specified)
Note  4.Typical values are for T A = +25°C and nominal supply voltages.
Note  5.This parameter is only sampled and is not 100% tested.
Read Operation (AC Test Conditions):
Output Load:  100pF + 1TTL Gate
Input Rise and Fall Times: ≤ 20ns
Input Pulse Levels:  0.45 to 2.4V
valid from是什么意思Timing Measurement Reference Levels:  Inputs  0.8 and 2V/0.8 and 2V
AC Waveforms:
ADDRESSES ADDRESSES VALID
CE
OE
OUTPUT HIGH Z
VALID OUTPUT
HIGH Z t CE
t ACC t
OH
t DE (Note 6)t DE (Note 7)
Note  6.OE may be delayed up to t ACC– t OE after the falling edge CE without impact on t ACC. Note7.t DF is specified from OE or CE whichever occurs first.
Read Mode:
The NTE2732A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs.  Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, indepen-dent of device selection.
Assuming that addresses are stable, address access time (t ACC) is equal to delay from CE to output (t CE).  Data is available at the outputs after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least t ACC–t OE.
Standby Mode:
The NTE2732A has a standby mode which reduces the active power current by 70%, from 125mA to 35mA.  The NTE2732A is placed in the standby mode by applying a TTL high signal to CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Output OR–Tieing:
Because NTE2732A’s are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection.  The two line control function allows:
a) the lowest possible memory power dissipation
b) complete assurance that output bus contention will not occur
To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE should be made a common connection to all devices in the array and connected to the READ line from the system control bus.
This assures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device.
Programming Operation:  (T A = +25°C ± 5°C, V CC = 5V ±5%, V PP = 21V ± 0.5V, Note 8, Note 9) DC and AC Operating Characteristics:
Note8.V CC must be applied simultaneously with or before V PP and removed simultaneously with or after V PP.  The NTE2732A must not be inserted into or removed from a board with V PP at 21 ± 0.5V or damage may occur to the device.
Note9.The maximum allowable voltage which may be applied to the V PP pin during programming is +22V.  Care must be taken when switching the V PP supply to prevent overshoot exceeding this 22V maximum specification.
AC Characteristics:
PROGRAM PROGRAM VERIFY
ADDRESSS N
ADRESSES
t AS
(Note 12)
DATA IN STABLE
ADD N
t DS (Note 12)
t DH (Note 12)
t OES (Note 12)
t OEH
(Note 12)
t PW
(45ms)
t VR
(Note 12)
t PRT (0.05)
t DV (Note 11)
PP V IL V IH V IL
DATA OUT VALID
ADD N
Hi Z
t AH (0)
t DF (0.13) Max
All times shown in ( ) are minimum and in µs unless otherwise specified.
Note12.The input timing reference level is 1V for V IL and 2V for V IH.
Note13.t OE and T DF are characteristics of the device but must be accommodate by the programmer.
Programming (CAUTION:  Exeeding 22V on pin (V pp) will damage the NTE2732A);
When delivered, and after each erasure, all bits of the NTE2732A are in the “1” state.  Data is introduced by selectively programming “0”s into the desired bit locations.  Although only “0”s will be programmed, both “1”s and “0”s can be presented in the data word.  The only way to change a “0”to a “1” is by ultraviolet light erasure.
The NTE2732A is in the programming mode when the OE/V PP input is at 21V.  It is required that a 0.1µF capacitor be placed across OE/V PP and ground to suppress spurious voltage transients which may damage the device.  The data to be programmed is applied 8 bits in parallel to the data output pins.  The levels required for the address and data inputs are TTL.
When the address and data are stable, a 50msec, active low, TTL program pulse is applied to the CE input.  A program pulse must be applied at each address location to be programmed.  You can pro-gram any location at any time–either individualy, sequentially, or at random.  The program pulse has a maximum width of 55msec.  The NTE2732A must not be programmed with a DC signal applied to the CE input.
Programming of multiple NTE2732A is in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements.  Like inputs of the paralleled NTE2732As may be c
onnected together when they are programmed with the same data.  A low level TTL pulse applied to the CE input programs the paralleled NTE2732As.
Program Inhibit:
Programming of multiple NTE2732As in parallel with different data is also easily accomplished.  Ex-cept for CE, all like inputs (including OE/V pp) of the parallel NTE2732As may be common.  A TTL level program pulse applied to a NTE2732As CE input with OE/V PP at 21V will program that NTE2732A.
A high level CE input inhibits the other NTE2732As from being programmed.
Program Verify:
A verify should be performed on the programmed bits to determine that they were correctly pro-grammed.  The verify is accomplished with OE/V PP and CE at V IL.
Erasure Operation:
The erasure characteristics of the NTE2732A are such that erasure begins when the cells are ex-pose
d to light with wavelengths shorter than approximately 4000 Angstroms (A).  It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000–4000 A range. Data shows that constant exposure to room level fluorescent lighting could erase a typical NTE2732A in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to the direct sunlight.  If the NTE2732A is to be exposed to these types of lighting conditions for ex-tended periods of time, it is suggested that opaque labels be put over the NTE2732A window to pre-vent unintentional erasure.
The recommended erasure procedure for the NTE2732A is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A).  The integrated dose (i.e. UV intensity x exposure time) for erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating.  The NTE2732A should be placed within 2.5cm of the lamp tubes during erasure.  Some lamps have a filter on their tubes which should be removed before era-sure.

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