10 /100Base-Tx/Fx Media Converter
Features
A 10/100BASE-TX/ 100BASE-FX converter  Built in a 10/100BASE-TX transceiver
Built in a PHY for 100BASE-FX
Built in a 2-port switch
– Pass all packets without address and
CRC check (optional)
– Supports modified cut-through frame
forwarding for low latency
– Supports pure converter mode data
forwarding for extreme low latency – Supports flow control for full and half
duplex operation
– Bandwidth control
– Forward 1600 bytes packet for
management
– Optional forward fragments
Built in 128Kb RAM for data buffer
Supports auto MDI-MDIX function
Supports link fault pass through function
Supports far end fault function
LED display for link/activity, full/half, 10/100  Built in a watchdog timer to monitor internal switch error
Supports EEPROM Configuration
negotiation auto
0.25u CMOS technology
Single 2.5V power supply
48-pin LQFP package
Support Lead Free package (Please refer to the Order Information) General Description
IP113C LF can be a 10/100BASE-TX to 100BASE-FX converter. It consists of a 2-port switch controller, a fast Ethernet transceiver and a PHY for 100BASE-FX. The transceivers in IP113C LF are designed in DSP approach with advance 0.25-um technology; this results in high noise immunity and robust performance.
IP113C LF not only supports store and forward mode, it also supports modified cut through mode and pure converter mode for low latency data forwarding. IP113C LF can transmit packet(s) up to 1600 bytes to meet requirement of extra long packets.
IP113C LF supports IEEE802.3x, collision base backpressure, and various LED functions, etc. These functions can be configured to fit the different requirements by feeding operation parameters via EEPROM interface or pull up/down resistors on specified pins.
Block Diagram
Revision History
Revision # Change Description
IP113C LF-DS-R01 Initial release.
IP113C LF-DS-R02 Remove Operation Junction Temperature.
IP113C LF-DS-R03 TP port should be linked at 100M full duplex when working at this mode.
IP113C LF-DS-R04 Add the order information for lead free package.
IP113C LF-DS-R05 Revise the diagram.
IP113C LF-DS-R06 TP_FORCE (Pin24) &X_EN(Pin29)
It is an input pin during reset period. The default value is latched at the end of reset. IP113C LF-DS-R07 Remove internal pull-high resistance & pull-low resistance on page 5.
Modify the IPL : pull-low and IPH : pull-high
IP113C LF-DS-R08 Add Power Pin description on Page10
Application Diagram
Applications
Un-managed converter
10B A S E_T/1
00B A S E-TX
100B A S E-F X
PIN Diagram
N C
F A S T _F W D
G N D R X IP L F P
G N D A 1
A V C C G N D T X O M A V C C R X IM F X R D M D I R E C T _W I R E V C C F X S D F X T D P F X T D M N C
T S M R E S E T B T S E X _E N L E D _F X _F E F _D E T / D U P L E X _M O D E L E D _T P _F D X L E D _T P _L IN K
L E D _F X _L IN K /  F X _F U L L  L E D _F X _S D / S P E E D _M O D E
V C C X 2G N D V C C O S C I S D A  S C L  /  A 0N C V C C B G R E S
V C C _IO G N D _IO G N D
L E D _F X _F D X  / A 2T X O P F X R D P A V C C N C
T P _F O R C E
L E D _T P _S P D
1. PIN Description
Type Description
pin
I Input
pin
O Output
IPL Input pin with internal pull-low resistor.
IPH Input pin with internal pull-high resistor.
Pin no. Label Type Description
Transceiver
5, 6 RXIP, RXIM I TP receive
8, 9 TXOP, TXOM O TP transmit
2 BGRES O
Band gap resistor
It is connected to GND through a 6.19k (1%) resistor in
application circuit.
18 FXSD I
100Base-FX signal detect
Fiber signal detect. It is an input signal from fiber MAU.
Fiber signal detect is active if the voltage on FXSD is higher
than the threshold voltage, which is 1.35v ±5% when VCC
is equal to 2.5v.
13, 14 FXRDP, FXRDM I Fiber receiver data pair
Common-mode voltage of FXRDP and FXRDM are
suggested to near 0.5x AVCC.
When voltage peak-to-peak>0.1V,FXRX could be
workable.
16, 17 FXTDP, FXTDM O Fiber transmitter data pair
FXTX with the external 100Ωresistor.
Common-mode voltage of FXTDP and FXTDM are
suggested to near 0.5x AVCC.
Swing of Voltage ≧ 0.8V.

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