Serial-GMII Specification The Serial Gigabit Media Independent Interface (SGMII) is designed to satisfy the following
requirements:
•Convey network data and port speed between a 10/100/1000 PHY and a MAC with
significantly less signal pins than required for GMII.
•Operate in both half and full duplex and at all port speeds. Change History
Revision Date Description
1.8April 27, 2005Add shim to the PHY transmit datapath to suppress TX_ER when TX_EN
is not asserted
1.7July 20, 20001Clarify data sampling and also the possible loss of the first byte of pream-
ble.
1.6Jan 4, 20001Added specifications for Cisco Systems Intellectual Property.
1.5Aug 4, 2000Specified the data pattern for the beginning of the frame (preamble, SFD)
for the frames sent from the PHY to make the PCS layer work properly.
1.4June 30, 2000Took out Jabber info, changed tx_Config_Reg[0] from 0 to 1 to make Auto-
Negotiation work
1.3April 17, 2000Increased allowable input and output common mode range. The output high
and low voltages were also increased appropriately. Added specification for
output over/undershoot. Added note about AC coupling and clock recovery.
1.2Feb 8, 2000Added timing budget analysis and reduced LVDS input threshold to +/- 50
mV.
1.1Nov 10, 1999Incoporated Auto-Negotiation Process for update of link status
1.0Oct. 14, 1999Initial Release
ef initions
MII – Media Independent Interface: A digital interface that provides a 4-bit wide datapath
between a 10/100 Mbit/s PHY and a MAC sublayer. Since MII is a subset of GMII, in this
document, we will use the term “GMII” to cover all of the specification regarding the MII
interface.
S fi on E15on 1.
GMII – Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide datapath between a 1000 Mbit/s PHY and a MAC sublayer. It also supports the 4-bit wide MII interface as defined in the IEEE 802.3z specification. In this document, the term “GMII”
covers all 10/100/1000 Mbit/s interface operations.
Ov erv iew
SGMII uses two data signals and two clock signals to convey frame data and link rate information between a 10/100/1000 PHY and an Ethernet MAC. The data signals operate at 1.25 Gbaud and the clocks operate at 625 MHz (a DDR interface). Due to the speed of operation, each of these signals is realized as a differential pair thus providing signal integrity while minimizing system noise.
Figure 1 illustrates the simple connections in a system utilizing SGMII.
The transmit and receive data paths leverage the 1000BASE-SX PCS defined in the IEEE 802.3z specification (clause 36). The traditional GMII data signals (TXD/RXD), data valid signals (TX_EN/RX_DV), and error signals (TX_ER/RX_ER) are encoded, serialized and output with the appropriate DDR clocking. Thus it is a 1.25 Gbaud interface with a 625 MHz clock. Carrier Sense (CRS) is derived/inferred from RX_DV, and collision (COL) is logically derived in the MAC when RX_DV and TX_EN are simultaneously asserted. There is a small block in the PHY transmit path to suppress TX_ER in full duplex mode when TX_EN is not asserted.
Control information, as specified in Table 1, is transferred from the PHY to the MAC to signal the change of the control information. This is achieved by using the Auto-Negotiation functionality defined in Clause 37 of the IEEE Specification 802.3z. Instead of the ability advertisement, the PHY sends the control information via its tx_config_Reg[15:0] as specified in Table 1 whenever the control information changes. Upon receiving control information, the MAC acknowledges the update of the control information by asserting bit 14 of its tx_config_reg{15:0] as specified in Table 1.
SGMII details source synchronous clocking; however, specific implementations may desire to recover clock from the data rather than use the supplied clock. This operation is allowed;however, all sources of data must generate the appropriate clock regardless of how they clock receive data.
1
S fi on  E 15on  1.The link_timer inside the Auto-Negotiation has been changed from 10 msec to 1.6 msec to ensure a prompt update of the link status.
Clearly, SGMII’s 1.25 Gbaud transfer rate is excessive for interfaces operating at 10 or 100Mbps. When these situations occur, the interface “elongates” the frame by replicating each frame byte 10 times for 100 Mbps and 100 types for 10 Mbps. This frame elongation takes place “above” the 802.3z PCS layer, thus the start frame delimiter only appears once per frame.The 802.3z PCS layer may remove the first byte of the “elongated” frame.
Bit Number tx_config_Reg[15:0] sent from the PHY to the MAC
tx_config_Reg[15:0] sent from the MAC to the PHY 15Link: 1 = link up, 0 = link down
0: Reserved for future use 14Reserved for Auto-Negotiation acknowledge as specified in 802.3z 1
130: Reserved for future use
0: Reserved for future use 12Duplex mode: 1 = full duplex, 0 = half duplex 0: Reserved for future use 11:10
Speed: Bit 11, 10:1 1 = Reserved
1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X 0 1 = 100 Mbps: 100BASE-TX, 100BASE-FX 0 0 = 10 Mbps: 10BASET, 10BASE2, 10BASE50: Reserved for future use
9:10: Reserved for future use 0: Reserved for future use 0
negotiation auto1
1
1 D fi on  of C on ol  I for on  p  b  l  v  t on fi 15
em entation S ec if ic ation
This section discusses how this SGMII interface shall be implemented by incorporating and modifying the PCS layer of the IEEE Specification 802.3z.
Signal Mapping at the PHY side
Figure 2 shows the PHY functional block diagram. It illustrates how the PCS layer shall be modified an
d incorporated at the PHY side in the SGMII interface.
At the receive side, GMII signals come in at 10/100/1000 Mbps clocked at 2.5/25/125 MHz.
The PHY passes these signals through the PHY Receive Rate Adaptation to output the 8-bit data RXD[7:0] in 125MHz clock domain. RXD is sent to the PCS Transmit State Machine to generate an encoded 10-bit segment ENC_RXD[0:9]. The PHY serializes ENC_RXD[0:9] to create RX and sends it to the MAC at 1.25 Gbit/s data rate along with the 625 MHz DDR RXCLK.
At the transmit side, the PHY deserializes TX to recover encoded ENC_TXD[0:9]. The PHY passes ENC_TXD[0:9] through the PCS Receive State Machine to recover the GMII signals.
In the mean time, Synchronization block checks ENC_TXD[0:9] to determine the synchronization status between links, and to realign if it detects the loss of synchronization.

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