Data Sheet
September 2007 TruePHY™ ET1011C
Gigabit Ethernet Transceiver
Features
n10Base-T, 100Base-TX, and 1000Base-T
gigabit Ethernet transceiver:
— 0.13 µm process
— 128-pin TQFP and 84-pin MLCC:
o RGMII, GMII, MII, RTBI, and TBI interfaces to
MAC or switch
— 68-pin MLCC:
o RGMII and RTBI interfaces to MAC or switch
n Low power consumption:
— Typical power less than 750 mW in 1000Base-T mode
— Advanced power management
— ACPI compliant wake-on-LAN support
n Oversampling architecture to improve signal integrity and SNR
n Optimized, extended performance echo and NEXT fil-ters
n All-digital baseline wander correction
n Digital PGA control
n On-chip diagnostic support
n Automatic speed negotiation
n Automatic speed downshift
n Single supply 3.3 V or 2.5 V operation:
— On-chip regulator controllers
— 3.3 V or 2.5 V digital I/O
— 3.3 V tolerant I/O pins (MDC, MDIO, COMA, RESET_N, and JTAG pins)negotiation auto
— 1.0 V or 1.1 V core power supplies
— 1.8 V or 2.5 V for transformer center tap
n JTAG
n ET1011C is a pin-compatible replacement for the
ET1011 device
n Commercial- and industrial-temperature versions avail-able Introduction
The LSI ET1011C is a Gigabit Ethernet transceiver fabri-cated on a single CMOS chip. Packaged in either an 128-pin TQFP, an 84-pin MLCC, or a
68-pin MLCC, the ET1011C is built on 0.13 µm technol-ogy for low power consumption and application in server and desktop NIC cards. It features single power supply operation using on-chip regulator controllers. The 10/100/ 1000Base-T device is fully compliant with IEEE® 802.3, 802.3u, and 802.3ab standards.
The ET1011C uses an oversampling architecture to gather more signal energy from the communication channel than possible with traditional architectures. The additional sig-nal energy or analog complexity transfers into the digital domain. The result is an analog front end that delivers robust operation, reduced cost, and lower power consump-tion than traditional architectures.
Using oversampling has allowed for the implementation of a fractionally spaced equalizer, which provides better equalization and has greater immunity to timing jitter, resulting in better signal-to-noise ratio (SNR) and thus improved BER. In addition, advanced timing algorithms are used to enable operation over a wider range of cabling plants.
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LSI Corporation
Data Sheet September 2007
Gigabit Ethernet Transceiver TruePHY ET1011C
<5Automatic 6Autonegotiation ................................................................7Carrier Sense (128-Pin TQFP and
84-Pin MLCC Only).....................................................8Regulator Control .............................................................8Resetting .
12Pin Diagram, 128-Pin TQFP ..........................................12Pin Diagram, 13Pin Diagram, 68-Pin MLCC ..........................................14Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC,
and .31Media-Dependent Interface:
32Clocking .34Regulator Control ...........................................................34Power, Ground, and 37Register 37Register .62Absolute
..62Recommended 62Device .67GMII 1000Base-T Transmit Timing
(128-Pin TQFP and 84-Pin MLCC Only)...................67GMII 1000Base-T Receive Timing
(128-Pin TQFP and 84-Pin MLCC Only)...................68RGMII 1000Base-T 69RGMII 1000Base-T Receive Timing .............................71MII 100Base-TX 73MII 100Base-TX Receive Timing .................................74MII 10Base-T Transmit Timing .....................................75MII 10Base-T 76Serial Management .79JTAG Timing ..................................................................80Package Diagram, 128-Pin TQFP ......................................81Package Diagram, 84-Pin MLCC ......................................82Package Diagram, 68-Pin MLCC ......................................83Ordering Information (84)
Table Page
Table 1. ET1011C Device Signals
by Interface, 128-Pin TQFP, 84-Pin
and 68-Pin MLCC (15)
Table 2. Multiplexed Signals on 20Table 3. GMII Signal Description (1000Base-T
Mode) (128-pin TQFP and
84-pin MLCC only) (22)
Table 4. RGMII Signal Description
(1000Base-T Mode) (23)
Table 5. MII Interface (100Base-TX and
10Base-T) (128-Pin TQFP and
84-Pin MLCC Only) (24)
Table 6. Ten-Bit Interface (1000Base-T)
(128-Pin TQFP and 84-Pin MLCC Only) (25)
Table 7. RTBI Signal Description
(1000Base-T Mode) (26)
Table 8. Management .27Table 9. 28Table 10. 29Table 11. LED ...................................................................31Table 12. Transformer 32Table 13. Clocking and Reset ............................................33Table 14. JTAG .34Table 15. Regulator 34Table 16. Supply V 35Table 17. Power, Ground, and 35Table 18. Cable 36Table 19. Register 37Table 20. Register 37Table 21. Control Register—38Table 22. Status Register—39Table 23. PHY Identifier Register 1—40Table 24. PHY Identifier Register 2—4
0Table 25. Autonegotiation Advertisement Register—
Address 4 (41)
Table 26. Autonegotiation Link Partner Ability
Register—Address 5 (42)
Table 27. Autonegotiation Expansion Register
—Address 6 (43)
Table of Contents  (continued)
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LSI Corporation 3
Data Sheet
September 2007Gigabit Ethernet Transceiver
TruePHY ET1011C
Table 28. Autonegotiation Next Page Transmit
Register—Address 7 (43)
Table 29. Link Partner Next Page Register —
Address 8 (44)
Table 30. 1000 Base-T Control Register—
Address 9 (45)
Table 31. 1000Base-T Status Register—
Address 10 (46)
Table 32. Reserved Registers—Addresses 11—14............47Table 33. Extended Status Register—47Table 34. Reserved Registers—Addresses 16—17............47Table 35. PHY Control Register 2—.48Table 36. MDI/49Table 37. MDI/MDI-X 49Table 38. Loopback Control Register—50Table 39. Loopback Bit (0.14) and Cable Diagnostic
Mode Bit (23.13) Settings for
Loopback Mode (50)
Table 40. RX Error Counter Register—51Table 41. Management Interface (MI) Control
Register—Address 21 (51)
Table 42. PHY Configuration Register—.52Table 43. PHY Control Register—53Table 44. Interrupt Mask Register—.54Table 45. Interrupt Status
Register—55Table 46. PHY Status Register—56Table 47. LED Control Register 1—.57Table 48. LED Control Register 2—.58Table 49. LED Control Register 3—.58Table 50. Diagnostics Control Register
(TDR Mode)—Address 30 (59)
Table 51. Diagnostics Status Register
(TDR Mode)—Address 31 (60)
Table 52. Diagnostics Control Register
(Link Analysis Mode)—Address 30 (61)
Table 53. MDI/MDI-X Configuration for 1000Base-T
with C and D Swapped/Not Swapped (61)
Table 54. Absolute 62Table 55. ET1011C Recommended
Operating Conditions (62)
Table 56. Device Characteristics—3.3 V
Digital I/O Supply (DVDDIO) (63)
Table 57. Device Characteristics—2.5 V
Digital I/O Supply (DVDDIO) (63)
Table 58. ET1011C Current Consumption
1000Base-T (64)
Table 59. ET1011C Current Consumption
100Base-TX (64)
Table 60. ET1011C Current Consumption
10Base-T (64)
Table 61. ET1011C Current Consumption
10Base-T Idle (65)
Table 62. ET1011C Current Consumption
Hardware Powerdown (65)
Table 63. ET1011C Current Consumption
Low Power Energy Detect (LPED) (65)
Table 64. ET1011C Current Consumption
Standby Powerdown (66)
Table 65. ET1011C Current Consumption
Software Powerdown (66)
Table 66. GMII 1000Base-T 67Table 67. GMII 1000Base-T Receive Timing..
..................68Table 68. RGMII 1000Base-T .69Table 69. RGMII 1000Base-T .70Table 70. RGMII 1000Base-T 71Table 71. RGMII 1000Base-T 72Table 72. MII 100Base-TX 73Table 73. MII 100Base-TX 74Table 74. MII 10Base-T 75Table 75. MII 10Base-T 76Table 76. Serial Management 77Table 77. Reset Timing ......................................................78Table 78. 79Table 79. 80Table 80. Ordering Information .. (84)
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4LSI Corporation
Data Sheet September 2007
Gigabit Ethernet Transceiver TruePHY ET1011C
Figure 1. ET1011C 5Figure 2. 9Figure 3. .9Figure 4. Replica and Line Driver 10Figure 5. External 10Figure 6. Pin Diagram for ET1011C in
128-Pin TQFP Package (Top View) (12)
Figure 7. Pin Diagram for ET1011C in
84-Pin MLCC Package (Top View) (13)
Figure 8. Pin Diagram for ET1011C in
68-Pin MLCC Package (Top View) (14)
Figure 9. ET1011C Gigabit Ethernet Card
Block Diagram (21)
Figure 10. GMII 22Figure 11. RGMII 23Figure 12. 24Figure 13. 25Figure 14. Reduced 26Figure 15. GMII 1000Base-T 67Figure 16. GMII 1000Base-T Receive Timing (68)
Figure 17. RGMII 1000Base-T Transmit Timing—
Trace Delay (69)
Figure 18. RGMII 1000Base-T Transmit Timing—
Internal Delay (70)
Figure 19. RGMII 1000Base-T Receive Timing—
Trace Delay (71)
Figure 20. RGMII 1000Base-T Receive Timing—
Internal Delay (72)
Figure 21. MII 100Base-TX 73Figure 22. MII 100Base-TX 74Figure 23. MII 10Base-T Transmit Timing ........................75Figure 24. MII 10Base-T 76Figure 25. Serial Management .77Figure 26. 78Figure 27. 79Figure 28. JTAG Timing.. (80)
Figure Figure (continued)
Data Sheet
September 2007
LSI Corporation 5
Gigabit Ethernet Transceiver
TruePHY ET1011C
Oversampling Architecture
The ET1011C architecture uses oversampling techniques to sample at two times the symbol rate. A fractionally spaced feed forward equalizer (FFE) adapts to remove intersymbol interference (ISI) and to shape the spectrum of the received signal to maximize the (SNR) at the trellis decoder input. The FFE equalizes the channel to a fixed target response. Oversampling enables the use of a fractionally spaced equal-izer (FSE) structure for the FFE, resulting in symbol rate clocking for both the FFE and the rest of the receiver. This provides robust operation and substantial power savings.
Automatic Speed Downshift
Automatic speed downshift is an enhanced feature of autone-gotiation that allows the ET1011C to:
n
Fallback in speed, based on cabling conditions or link partner abilities.
n Operate over CAT-3 cabling (in 10Base-T mode).n
Operate over two-pair CAT-5 cabling (in 100Base-TX mode).
For speed fallback, the ET1011C first tries to autonegotiate by advertising 1000Base-T capability. After a number of failed attempts to bring up the link, the ET1011C falls back to advertising 100Base-TX and restarts the autonegotiation process. This process continues through all speeds down to 10Base-T. At this point, there are no lower speeds to try and so the host enables all technologies and starts again.PHY configuration register, address 22, bits 11 and 10
enable automatic speed downshift and specifies if fallback to 10Base-T is allowed. PHY control register, address 23, bits 11 and 12 specify the number of failed attempts before downshift (programmable to 1, 2, 3, or 4 attempts).

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