An 'intelligent' approach to dummy fill
jsessionidBy David White and Bob Moore , EEdesign
Jan 03, 2005 (12:00 PM EST)
URL: design/article/showArticle.jhtml?articleId=56700224
With the advent of copper interconnect and its susceptibility to topographical thickness variation, and with feature sizes on chips shrinking at each new process node, the impact of chemical mechanical polishing (CMP) on chip design is increasing.
The solution to date is for chip designers and manufacturers to adopt the use of dummy fill and line slotting to create a uniform interconnect layout pattern that minimizes topographical variation (and therefore the electrical variation of the wires). Manufacturers create design rules for dummy fill and slotting that specify the fill characteristics and allowable locations. Dummy fill and slotting using these rules can be applied by the design team, the mask shop or manufacturing.
The impact of dummy fill on delay and cross-talk is increasingly difficult to quantify, and the ability of simple design rules to minimize the thickness variation is becoming more questionable as
geometries shrink. A new technology has recently emerged that predicts the interconnect thickness for all the nets on the chip. This technology can therefore be used to generate an intelligent dummy fill which dramatically reduces topographical variation and minimizes the parasitic capacitance that results from fill insertion.
Copper interconnect thickness variation
One of the side effects of introducing copper as the interconnect material of choice for 0.13 micron designs and below was copper's susceptibility to topographical variation during the deposition and polishing steps of the manufacturing process. These topographic variations are caused by pattern-dependent layout features within the die (see Figure 1).
Physical interconnect variations become electrical parasitic variations impacting a chip's timing, power consumption and signal integrity. The magnitude of the variation is communicated to designers through technology files that provide best-case/worst-case/nominal thickness
information. RC extraction tools such as Star-RCXT, Assura, Fire and Ice, Net-An, and others convert the physical dimensions of interconnect in a design to electrical parasitics.
Figure 1 — Layout pattern-dependent impact on interconnect thickness
The magnitude and uncertainty of the interconnect thickness variation presents a challenge for designers because they need to verify that their design performs to specification for the range and combinations of best-case to worst-case conditions. The size of the guard-band is directly proportional to the interconnect thickness variation, and the percentage of interconnect variation has been increasing with each new process node.
Although this guard-band will never be completely eliminated, the magnitude needs to be controlled and minimized. Excessively conservative guard-bands lead to significant limits on performance and/or power consumption.
As process nodes advance to increasingly smaller dimensions, the cross-sectional interconnect area will continue to shrink, which leads to proportional increases in resistance. In the transition from the 90
nm to 65nm node alone, where interconnect width and thickness are both reduced by 29%, the cross-sectional area will be reduced by almost 50%. As the following formulation illustrates, this reduction results in a 100% increase in resistance for the same line length and resistivity.
Even if line length were reduced, it would require a 50% decrease to cancel the increase in resistance. The decrease in cross-sectional area similarly impacts the effects of process-induced thickness and width variation with each technology node.
Consider a damascene process that produces a 15% variation in minimum feature thickness at
90nm. This process would similarly produce a 20% variation in the minimum feature thickness at 65nm, even if the absolute thickness variation remained the same. At the same time, demand for performance is increasing (higher clock speeds) and power consumption is decreasing (longer
battery life) which makes meeting specifications even more challenging.
Manufacturing has done a number of things to minimize the interconnect topography, including more advanced and complex polishing processes and a new generation of selective polishing chemicals and pads. The dummy fill and slotting methodology has become a standard procedure, especially for processes with copper interconnect (0.13 and below). The relatively simple dummy fill algorithms used by most fabs are facing new challenges to keep up with the shrinking line widths and potential electrical impacts.
The current solution — dummy fill and slotting
Today, dummy fill and slotting are used to create a more uniform density, which theoretically will lead to a more planar die surface. Portions of a chip that are outside a density range will have dummy fill inserted to reach the target density. Similarly, lines (or interconnect) on the die that exceed a target width may have slots inserted again to achieve a target density. Rules provided by the manufacturer, as part of the Process Design Kit, determine when and where dummy fill or slotting should be applied. Creating a "universal" dummy fill algorithm is an increasingly complex task that is challenging to verify even for the most advanced process teams. The algorithm ideally should be tested on a variety of product designs but this is often not done, since it involves a manufacturing and testing step for each design, with resulting expense and time and production resources consumed.
Once an algorithm has been defined, process engineers are reluctant to make any changes, because determining the impact of a change requires another iteration of dummy insertion, wafer manufacturing and measurement for each design to be tested. Therefore algorithms in use today often were defined on older processes and may be several years old. In some cases, fill approaches were created for oxide CMP processes and were not optimized for copper CMP planarity issues.  So as not to redefine an algorithm, designers may specify areas of the chip and particular metal layers where dummy fill is "blocked" so that any dummy fill electrical impact is minimized. Designers may also adjust line spacing to "get around" the dummy insertion algorithm. This is particularly important for analog or RF designs, and the analog or RF blocks in mixed signal designs.
Today, the dummy fill step is usually done after (or in some cases in parallel with) the final verification step as part of mask data preparation. For fabs, the actual dummy fill and slotting insertion is typically done by the mask shop. The result is that most designers are unable to account for the impact of dummy fill and slotting on their design.
The growing design problem
Until the 90nm process node, designers have been able essentially to ignore the impact of dummy fill
because the dummy fill "rules" have been adequate to provide the necessary uniformity, and the electrical impact of dummy fill has been negligible. However, at 90nm and beyond, designers either will have to become more cognizant of dummy fill or to revise the design flow to provide a more intelligent dummy fill insertion methodology.
The entire dummy fill and slotting "insertion" methodology is based on having accurate thickness information for the entire product chip. The methodology of using density and/or line width as a proxy for thickness will no longer suffice at the advanced process nodes. A number of factors contribute to this problem of inaccurate interconnect thickness predictions, including:  z Copper plating (ECD) impact on thickness
z Multi-layer topography impact
z Long range (2-4mm) CMP effects
A paper recently presented at the VLSI Multi-level Interconnect Conference ("Deficiencies of Copper CMP Models Based on Lookup Tables" by T. Smith, et al) describes these issues in more detail. As you can see from Figure 2, which represents a product chip manufactured on a 90nm process, there is a very poor correlation between density or line width and the amount of copper loss.
Figure 2 — Plot showing the poor correlation between density or line width and copper loss
The impact of dummy fill on capacitance also increasingly needs to be taken into consideration. The most common approach to dummy fill is to use floating metal, which has less capacitance impact than grounded metal fill. Different shapes and configurations of dummy fill also are used, not only to create a more uniform density but also to minimize the capacitance.
The most advanced dummy fill algorithms use a variety of sizes, shapes (square, rectangle), configurations (symmetric, asymmetric) and spacing (maintain constant density by increasing size and spacing proportionally). Each iteration of any of the multiple factors above would require modifying a te
st design, creating a mask, manufacturing wafers and measuring the results (both physically and electrically). An iteration would take weeks, not to mention the costs of the mask and of tying up valuable production equipment.
Despite good intentions, the actual impact of dummy fill on capacitance is sometimes ignored or unknown during the design process, and can potentially be overshadowed by unexpected increases in resistance due to interconnect thickness thinning which exceeds the dummy fill capacitance impact. For example, Figure 3 shows an analog IP block that is devoid of dummy fill (to minimize capacitance) but actually has a large resistance impact because the whole area was eroded more than expected during the CMP process.
Figure 3 — Analog IP block thickness vs. dummy capacitance impact
Resolution Enhancement Technology (RET) issues with dummy fill have been discussed and addressed in other articles and papers. The objective there is to identify which objects are dummy fill so that no time is wasted on RET to recreate the identical shape on the chip. Of course this raises questions about what impact the different shape might have on the interconnect topography and capacitance.
Another more common challenge is the increasing use of intellectual property (IP). Since the IP block may have been created for another design, was the same dummy fill strategy assumed? Will the same topography be present and the same capacitance impact be felt, or could the IP behave differently depending on where it is located?
IP next to an SRAM is likely to have different interconnect erosion than the same IP next to a logic block or an analog block, for example. This issue may not be quite as sensitive for digital IP, but analog IP could be problematic.
Yet another challenge results from the increase in the number of interconnect levels. Variation in

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