EtronTech
EM639165
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
8Mega x 16bits SDRAM
Preliminary (Rev 1.0, 2/2001)
Features
•Single 3.3 ± 0.3V power supply •Fast clock rate
- PC133: 133 MHz (CL3)- PC100: 100 MHz (CL2)
•Fully synchronous operation referenced to clock rising edge
•4-bank operation controlled by BA0, BA1 (Bank Address)
•Programmable Mode registers -/CAS Latency: 2 or 3
-Burst Length: 1, 2, 4, 8 or full page -Burst Type: interleaved or linear burst •Byte Control – DQML and DQMU •Random column access
•Auto precharge / All banks precharge controlled by A10
•Auto and self-refresh
•Self-refresh mode: standard and low power •4096 refresh cycles/64ms •Interface:  LVTTL
•54-pin 400 mil plastic TSOP II package
Key Specifications
EM639165
- 75/8
t CK2Clock Cycle time (min., CL=2)10/10 ns t CK3Clock Cycle time (min., CL=3)7.5/8 ns t AC2Access time (max., CL=2)6/6 ns t AC3Access time (max., CL=3)  5.4/6 ns t RAS Row Active time (max.)45/48 ns t RC
Row Cycle time(min.)
67.5/70 ns
Overview
EM639165 is a high-speed Synchronous Dynamic Random Access Memory (SDRAM), organized as 4banks x 2,097,152 words x 16 bits. All inputs and outputs are referenced to the rising edge of CLK.
It achieves very high-speed data rates up to 133MHz, and is suitable for main memories or graphic memories in computer systems. For handheld device application, we also provide a low power option, with self-refresh current under 800 µA.
Pin Assignment (Top View)
Part Number
Speed Grade Self refresh current (Max.)
EM639165TS-75PC133/CL3  2 mA EM639165TS-75L PC133/CL3800 µA EM639165TS-8PC100/CL2  2 mA EM639165TS-8L
PC100/CL2
800 µA
BLOCK DIAGRAM
A0-11BA0,1/CS/RAS/CAS/WE
CLK CKE DQM
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deac-tivated after the burst read (auto-precharge, READA ).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. T otal data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA ).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally . After this command, the banks are precharged automatically .
BASIC FUNCTIONS
active下载The EM639165 provides basic functions, bank (row)activate, burst read / write, bank (row)  precharge,  and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and    /WE at CLK rising edge. In addition to 3 signals, /CS
,CKE  and A10 are used as chip select, refresh opt ion, and precharge option, respectively .
To know the detailed definition of commands, please see
the command truth table.
/
CS
Chip Select : L=select, H=deselect /RAS
Command /CAS
Command /WE
Command
CKE
Refresh Option @ refresh command
A10
Precharge Option @ precharge or read/write command
CLK define basic command

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