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uPI Semiconductor Corp., www.upi-semi Rev. F01, File Name: uP6101-DS-F0100
5V/12V Synchronous-Rectified
Buck Controller
The uP6101 is a compact synchronous-rectified buck controller specifically designed to operate from 5V or 12supply voltage and to deliver high quality output voltage as low as 0.6V (uP6101A) or 0.8V (uP6101B/C). This (P)SOP-8 device operates at fixed 300kHz (uP6101A/B) or 200kHz (uP6101C) frequency and provides an optimal level of integration to reduce size and cost of the power supply.This controller integrates internal MOSFET drivers that support 12V+12V bootstrapped voltage for high efficiency power conversion. The bootstrap diode is built-in to simplify the circuit design and minimize external part count.Other features include internal softstart, under voltage protection, over current protection and shutdown function.With aforementioned functions, this part provides customers a compac
t, high efficiency, well-protected and cost-effective solutions. This part comes to SOP-8 and PSOP-8 packages.
Operates from 5V or 12V Supply Voltage    3.3V to 12V V IN  Input Range
0.6V or 0.8V to 80% of V IN  Output Range  0.6V or 0.8V Internal Reference
1.5% Over Line Voltage and Temperature
Simple Single-Loop Control Design
Voltage-Mode PWM Control  Fast Transient Response  High-Bandwidth Error Amplifier
0% to 80% Duty Cycle
Lossless, Programmable Overcurrent Protection
Uses Lower MOSFET R DS(ON)
300/200kHz Fixed Frequency Oscillator  Internal SoftStart
Integrated Boot Diode
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c n e u q e r f g n i h c t i w s z H k 002 Power Supplies for Microprocessors or
Subsystem Power Supplies  Cable Modems, Set Top Boxes, and DSL
Modems  Industrial Power Supplies; General Purpose
Supplies  5V or 12V Input DC-DC Regulators
Low-Voltage Distributed Power Supplies
Pin Configuration & Typical Application Circuit
General Description
Applications
Ordering Information
Features
Note: uPI products are compatible with the current IPC/JEDEC J-STD-020 and RoHS requirements. They are 100%matte tin (Sn) plating and suitable for use in SnPb or Pb-free soldering processes.
PHASE BOOT COMP/EN FB VCC
UGATE GND LGATE
SOP-8
PHASE BOOT COMP/EN FB VCC
UGATE GND LGATE
PSOP-8
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uPI Semiconductor Corp., www.upi-semi Rev. F01, File Name: uP6101-DS-F0100
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uPI Semiconductor Corp., www.upi-semi Rev. F01, File Name: uP6101-DS-F0100
Functional Block Diagram
VCC GND
LGATE
PHASE
UGATE
BOOT
FB COMP/EN
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uPI Semiconductor Corp., www.upi-semi Rev. F01, File Name: uP6101-DS-F0100
The uP6101 is a compact synchronous-rectified buck controller specifically designed to operate from 5V or 12supply voltage and to deliver high quality output voltage as low as 0.6V (uP6101A) or 0.8V (u
P6101B/C). This (P)SOP-8 device operates at fixed 300kHz (uP6101A/B) or 200kHz (uP6101C) frequency and provides an optimal level of integration to reduce size and cost of the power supply.This controller integrates internal MOSFET drivers that support 12V+12V bootstrapped voltage for high efficiency power conversion. The bootstrap diode is built-in to simplify the circuit design and minimize external part count.Supply Voltage
The VCC pin receives a well-decoupled 4.5V to 13.2V supply voltage to power the control circuit, the lower gate driver and the bootstrap circuit for the higher gate driver. A minimum 0.1uF ceramic capacitor is recommended to bypass the supply voltage. Place the bypassing capacitor physically near the IC.
An internal linear regulator regulates the supply voltage into a 4.2V voltage VDD for internal control logic circuit. No external bypass capacitor is required for filtering the VDD voltage.
The uP6101 integrates MOSFET gate drives that are powered from the VCC pin and support 12V+12V driving capability. A bootstrap diode is embedded to facilitate PCB design and reduce the total BOM cost. No external Schottky diode is required. Converters that consist of uP6101 feature high efficiency without special consideration on the selection of MOSFETs.Power On Reset and Chip Enable
A power on reset (POR) circuitry continuously monitors the supply voltage at VCC pin. Once the rising POR threshold is exceeded, the uP6101 sets itself to active state and is ready to accept chip enable command. The rising POR threshold is typically 4.2V at VCC rising.The COMP/EN is an multifunctional pin: control loop compensation and chip enable as shown in Figure 1. An Enable Comparator monitors the COMP/EN pin voltage for chip enable. A signal level transistor is adequate to pull this pin down to ground and shut down the uP6101. A 80uA current source charges the external compensation network with 0.45V ceiling when this pin is released. If the voltage at COMP/EN pin exceeds 0.3V, the uP6101 initiates its softstart cycle.
The 80uA current source keeps charging the COMP pin to its ceiling until the feedback loop boosts the COMP pin higher than 0.45V according to the feedback signal. The current source is cut off when V COMP  is higher than 0.45V
during normal operation.
Figure 1. Chip Enable Function
SoftStart
A built-in Soft Start is used to prevent surge current from power supply input during turn on (referring to the Functional Block Diagram). The error amplifier is a three-input device.Reference voltage V REF  or the internal soft start voltage SS whichever is smaller dominates the behavior of the non-inverting inputs of the error amplifier. SS internally ramps up to 0.6V in 2.7ms for uP6101A (to 0.8V in 3.4ms for uP6101B; to 0.8V in 5.4ms for uP6101C) after the softstart cycle is initiated. The ramp is created digita
lly, so there will be 100 small discrete steps. Accordingly, the output voltage will follow the SS signal and ramp up smoothly to its target level.
The SS signal keeps ramping up after it exceeds the internal 0.6 (0.8V for uP6101B/C) reference voltage. However, the internal 0.6V (0.8V for uP6101B/C) reference voltage takes over the behavior of error amplifier after SS > V REF . When the SS signal climb to its ceiling voltage (4.2V), the uP6101claims the end of softstart cycle and enable the under voltage protection of the output voltage.
Figure 2 shows  a typical start up interval for uP6101A where the COMP/EN pin has been released from a grounded (system shutdown) state.
The internal 80uA current source starts charge the compensation network after the COMP/EN pin is released from grounded at T1. The COMP/EN exceeds 0.3V and enable the uP6101A at T2. The COMP/EN continues ramping up and stays at 0.45V before the SS starts ramping up at T3. The uP6101A initializes itself such as current limit level setting (see the relative section) during the time interval  between T2 and T3. The output voltage follows the
Functional Description
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uPI Semiconductor Corp., www.upi-semi Rev. F01, File Name: uP6101-DS-F0100
internal SS and ramps up to its final level during T3 and T4.At T4,  the reference voltage V REF  takes over the behavior of the error amplifier as the internal SS crosses V REF . The internal SS keeps ramping up and stay at 4.2V at T5, where the uP6101A asserts the end of softstart cycle.
COMP
0.5V/Div
LGATE 10V/Div
V OUT  0.5V/Div Time 1ms/Div
Figure 2. Softstart Behavior of uP6101A.
Power Input Detection
The uP6101 detects PHASE voltage for the present of power input when the UGATE turns on the first time. If the PHASE voltage does not exceed 2.0V when the UGATE turns on,the uP6101 asserts that power input in not ready and stops the softstart cycle. However, the internal SS continues ramping up to VDD. Another softstart is initiated after SS ramps up to VDD. The hiccup period is about 8ms. Figure 3 shows the start up interval where V IN  does not present initially.
V IN 5V/Div
LGATE 10V/Div
V OUT  0.5V/Div
Ix 1A/Div
Time 1ms/Div
Figure 3. Softstart where V IN  does not Present Initially.Output Voltage Selection
The output voltage can be programmed to any level between the 0.6V internal reference (0.8V for uP6101B/C), up to the 80% of V IN  supply. The lower limitation of output voltage is caused by the internal reference. The upper limitation of the output voltage is caused by the maximum available duty cycle (80% typical). This is to leave enough time for overcurrent detection. Output voltage out of this range is not allowed.
An voltage divider sets the output voltage (refer to the Typical Application Circuit on page 1 for detail). In real applications, choose R1 in 100Ω ~ 10k Ω range and choose appropriate R2 according to the desired output voltage.
2R 2
R 1R V 6.02R 2R 1R V V REF OUT +×=+×
=      uP6101A 2
R 2
R 1R V 8.02R 2R 1R V V REF OUT +×=+×
=      uP6101B/C Overcurrent Protection (OCP)
The uP6101 detects voltage drop across the lower MOSFET (V PHASE ) for overcurrent protection when it is turned on. If V PHASE  is lower than the user-programmable voltage V OCP ,the uP6101 asserts OCP and shuts down the converter.The OCP level can be calculated according the on-resistance of the lower MOSFET used.
)
ON (DS OCP OCP R V I −
=(A)
Functional Description
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uPI Semiconductor Corp., www.upi-semi Rev. F01, File Name: uP6101-DS-F0100
Functional Description
Connecting a resistance from LGATE to GND selects the appropriate V OCP  as shown in Table 1. Also shown in Table 1 is OCP level if a lower MOSFET with 10m Ω R DS(ON) is used.
Table 1. OCP Level Selection
R P C O (Ω)n e p o k 24k 62k 01V P C O )V m (573-003-522-051-I P C O )
A (5
.735
25
.225
1When programming the OCP level, take into consideration the conditions that affect R DS(ON) of the lower MOSFET ,including operation junction temperature, gate driving voltage and distribution. Consid
er the R DS(ON)  at maximum operation temperature and lowest gate driving voltage.
Another factor should taken into consideration is the ripple of the inductor current. The current near the valley of the ripple current is used for OCP , resulting the averaged OCP level a little higher than the calculated value.

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