Correlating and simulating RCLk and substrate
parasitics in RFIC Circuit Design
LihYing Ching , Paul Wen, Sophie Sheng  & Longle Shi  SMIC1, Pudong, Shanghai, China Venkat Ramasubramanian, Tao Li, & Bob Mullen , Cadence Design Systems, San Jose, California USA Abstract
Often, there is a need to simulate RFIC designs with RCLk2 and substrate parasitics to accurately represent high frequency affects in actual silicon.  Parasitics can either be RCLk parasitics from the surface layers of the chip, especially from metallization routing and coupling, or from RC parasitics of the silicon substrate. Substrate parasitics are especially important if considering the affects of substrate noise injection and subtle interactions of high frequency ground loops.  For sensitive circuits, such as a VCO in a PLL, it is important to consider the possibility of substrate parasitic coupling. Close-by digital circuits can inject current into the substrate.  Before parasitics can be simulated in a particular semiconductor process it is first necessary to characterize the process, create, and calibrate technology rule files. This process can be tedious to complete and then correlate to silicon. Once the process is proven, parasitic extraction can be usefully used in RFIC design.
The steps of preparing and correlating RLCk and substrate parasitics with the SMIC .18um CMOS RF/M
S process using Cadence’s QRC (formerly AssuraRF) extraction tools are discussed. Shown are the correlations of test structures to silicon and of a  VCO circuit block.
Introduction
For RFIC designs working into  the GHz range, it is important to include not only the RC parasitics of metallization routing, as is done in the megahertz frequency range of AMS circuits, but  to include also the L and k (mutual inductance) transmission affects. This is especially true when simulating the high frequency signal paths in a transceiver. In the case of on-chip spiral inductors, it is important to extract the full RCLk and substrate parasitics together with other circuits. This can be done by an EM extraction of the inductor and then add to the other parasitics extracted into a combined RCLk + substrate netlist. Or, it is possible to extract the inductor and all the parasitics together which is sometimes preferred, since the mutual coupling of all components can be realized in one netlist. Adding the RC substrate parasitics adds additional parasitics not normally modeled. One major issue with extracting parasitics, which is fundamentally easy to do along with the fact that parasitic modeling can be accurate and correlated, is converging on a simulation solution. This is the biggest issue working with parasitic netlists.
1 SMIC = Semiconductor Manufacturing International Corporation
2 R=Resistance, C=Capacitance , L=Inductance, and k=mutual inductance
Setting up to Simulate with Extracted Parasitics
Setting up a semiconductor process to simulate parasitics starts with PDK3 technology files. From this, additional RC and SNA extraction technology rules and files are added to allow for a smooth flow going from schematic capture, layout, LVS and create an extracted parasitic netlist for re-simulation. To properly characterize a semiconductor process for parasitics, technology details such as metallization layers, resistivities, thicknesses, dielectric layers, and the substrate profiles for Substrate Noise Analysis (SNA) are needed. SNA requires cross-sections of the carrier doping profiles from the top of junctions down thru to the substrate. Each important region in process needs a cross-section.  Typical, for an nwell CMOS process, there can be up to 20-25 separate profiles which can include low and high voltage CMOS devices as well as isolation regions.  Shown in Fig. 1 are the basic transistor cross-sections.
Fig. 1 – Typical CMOS process profiles (black lines)
For the technology files, specific process information needs to be captured in a particular format to support the extraction tools.  The technology files with associated setups are supplied by the foundry supporting the PDK and represent significant work. The substrate profiles are usually encrypted and co
nsidered proprietary.  However it is helpful to known what profiles are supported.  Extracting RCLk parasitic is involved with metallization layers and trace routing, whereas, SNA deals with the RC substrate parasitic. Since there are 20+ profiles in a typical CMOS process, the parasitic over each region are different. For frequencies less than corner-frequency(f c ~17GHz for 10 ohm-cm doping level that is typically used for p-type substrate), the parasitics are practically all resistive. At higher frequencies, capacitance becomes dominant and the complete RC grid is important.  The substrate grid used for SNA is illustrated in Fig. 2.
3 PDK is a  “Process Design Kit” which is a Cadence built device library to support the process
Fig. 2 – Substrate process grid profile
Correlating Simulation to Silicon Measurements
To correlate simulation to actual silicon measurements, it is necessary to have a precision lab setup from de-embedding to actual measurements because at GHz frequency the effects of probe tips and ground loops from measurement can throw off the measurements. The recent opening of SMIC RF-lab in Shanghai with joint partnership came just in time to meet such demands. Fig. 3 shows the 40GHz Network-Analyzer (Agilent E8363B) and high-end Wafer-Prober (Cascade S300) used in this characterization work. After careful system calibration and de-embedding procedure, the transmission coefficient (magnitude of S21 in dB) is taken as a gauge of the noise coupling between the two ports.
To correlate each profile, parasitic test structures are created to validate the
extraction accuracy. From this, circuit measurements can be evaluated and correlated Fig. 3 - Measurement Setup. Shown are Agilent E8363B Network-Analyzer and Cascade S300.
accordingly. Fig. 4 shows the layout of test structures for substrate-coupling purpose. Fig.
5 shows the fabricated device under S-parameter testing.
Fig. 4 – SNA test structures used to correlate simulation to measurement
Fig. 5 - Device under S-Parameter testing.
The following discusses the results obtained so far.
I)Coupling between P-taps in P-well
Fig. 6 illustrates the coupling from a pair of p-taps in P-well with varying degree of separation, where both measurements and simulation(RCLk + substrate coupling) results are compared. Each tap is a square of 10um in length. And, the pair of taps is bounded by P+Guardring that 1) sets the substrate potential at ground; 2) defines investigation space. As shown, the coupling decreases with physical separation, a characteristic for non-epi process. Up to 20GHz, the frequency response is basically flat, and thus indicating predominantly resistive coupling. In the cases for the shorter separation(D50, D100), it is
reported
noted the  discrepancy between measurement and simulation increases with frequency, yet to be understood.
meas si Layout view 50um m si meas 100um
m meas si 150um
m Cross-sectional view Fig. 6 - Substrate coupling between a pair of P-taps in P-well as function of separation – measurements versus
simulations
II) Coupling between N-taps in P-well
Fig. 7 illustrates the measured and simulated results for a pair of n-taps with 100um separation. Although agreement at low frequencies(<2GHz) is good, the deviation widens with increasing frequency and the cause is yet to be identified. In this case, n-type diode devices are involved in the coupling process beyond the substrate resistive network and thus simulation accuracy also hinges on how well diode is modeled.
Layout View Cross-Sectional  View meas sim
Fig. 7 - Substrate coupling between a pair of N-taps in P-well – measurements versus simulation.

版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。