专利名称：FORMATION OF METAL AND POLYSILICON DUBLE LAYER GATE
reactive metal发明人：NENGUUUEI U
申请号：JP9131990
申请日：19900405
公开号：JPH0362970A
公开日：
19910319
专利内容由知识产权出版社提供
摘要：PURPOSE: To reduce the gate sheet resistance of a VSLI device by a method wherein a metal layer is formed after finishing a heat treatment completely in order to avoid oxidation and silicification between a metal and an underlying polysilicon layer and polysilicon underlying a gate linking part sustains the electrical characteristics of an ordinary gate. CONSTITUTION: At first, a recessed isolation structural part 1 having low defect density is formed on a substrate 5 under the fringe of a field oxide by local thermal oxidation. Polysilicon is then deposited by 350-500nm by low pressure chemical vapor deposition and POCl3 is doped by diffusion or ion implantation. After defining a gate linking part 3 by lithography or polysilicon etching, a small implantation and oxide side wall isolator forming part 4 is formed to set a slightly doped drain structure. An isolator is formed by reactive ion etching following to CVD oxide deposition with high etching anisotropy in order to preserve a corner oxide at the edge of polysilicon gate linking part.
申请人：IND TECHNOL RES INST
更多信息请下载全文后查看

版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。