字符串长度和占用内存字节
Table 61: DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based
Table 62: DDR3L Derating Values for t DS/t DH – AC160/DC90-Based
Table 63: DDR3L Derating Values for t DS/t
DH – AC135/DC100-Based
8Gb: x4, x8, x16 DDR3L SDRAM Data Setup, Hold, and Derating
Table 65: DDR3L Minimum Required Time t VAC Above V IH(AC) (Below V IL(AC)) for Valid DQ Transition
Note:  1.Rising input signal shall become equal to or greater than V IH(AC) level and Falling input
signal shall become equal to or less than V IL(AC) level.8Gb: x4, x8, x16 DDR3L SDRAM Data Setup, Hold, and Derating

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