Advanced Encryption Standard / Rijndael
IP Core
Author: Rudolf Usselmann
rudi@asics.ws
www.asics.ws
Rev. 1.1
November 12, 2002
Revision History
Rev.Date Author Description
Initial Release
1.011/9/02Rudolf
Usselmann
1.111/12/2002RU Fixed Several Typos
ASICS.ws AES Rijndael IP Core November 12, 2002
1
Introduction Simple AES/Rijndael IP Core. I have tried to create a implementation of this standard that would fit in to a low cost FPGA, like the Spartan IIe series from Xil-
ignore subsequent bad blocksinx, and still would provide reasonably fast performance.
This implementation is with a 128 bit key expansion module only. Implementa-tions with different key sizes (192 & 256 bits) and performance parameters (such
as a fully pipelined ultra-high -speed version) are commercially available from
ASICS.ws (www.asics.ws).
This document will describe the interface to the IP core. It will not talk about the AES standard itself.
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Architecture
The AES Rijndael core consists of two blocks: 1) The AES Cipher block
which performs encryption; 2) The AES Inverse Cipher block which performs
decryption. Both blocks instantiate the same key expansion block.
2.1.AES Cipher Core
Below figure illustrates the overall architecture of the AES Cipher core. Figure 1: Cipher Core Architecture Overview
The AES cipher core consists of a key expansion module, an initial permuta-
tion module, a round permutation module and a final permutation module. The
round permutation module will loop internally to perform 10 iteration (for 128 bit
keys).
Key Expansion
Initial Permutation Round Permutation Final Permutation Control ld key text_in text_out
done
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4 of 9Rev. 1.1 www.asics.ws 2.2.AES Inverse Cipher Core
Below figure illustrates the overall architecture of the AES Inverse Cipher
core. Figure 2: Inverse Cipher Core Architecture Overview
The AES inverse cipher core consists of a key expansion module, a key rever-
sal buffer, an initial permutation module, a round permutation module and a final
permutation module.
The key reversal buffer first stores keys for all rounds and then presents them in
reverse order to the inverse cipher rounds.
The round permutation module will loop internally to perform 10 iteration (for
128 bit keys).
Key Expansion Initial Permutation Round Permutation Final Permutation Control kld
key text_in text_out
kdone Key reverse buffer
done
ld

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