Chapter 1 Computer System Overview
Review Questions
1.1 List and briefly define the four main elements of a computer.
1.2 Define the two main categories of processor registers.
1.3 In general terms, what are the four distinct actions that a machine instruction can specify?
1.4 What is an interrupt?
1.5 How are multiple interrupts dealt with?
1.6 What characteristics distinguish the various elements of a memory hierarchy?
1.7 What is cache memory?
1.8 List and briefly define three techniques for I/O operations.
1.9 What is the distinction between spatial locality and temporal locality?
1.10 In general, what are the strategies for exploiting spatial locality and temporal locality?
Problemsignore subsequent bad blocks
1.1 Suppose the hypothetical processor of Figure 1.3 also has two I/O instructions:
0011 = Load AC from I/O
0111 = Store AC to I/O
In these cases, the 12-bit address identifies a particular external device. Show the program execution (using format of Figure 1.4) for the following program:
1. Load AC from device 5.
2. Add contents of memory location 940.
3. Store AC to device 6.
Assume that the next value retrieved from device 5 is 3 and that location 940 contains a value of 2.
1.2 The program execution of Figure 1.4 is described in the text using six steps. Expandthis description to show the use of the MAR and MBR.
1.3 Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields. The first byte contains the opcode and the remainder an immediate operand or an operand address.
a. What is the maximum directly addressable memory capacity (in bytes)?
b. Discuss the impact on the system speed if the microprocessor bus has
1. a 32-bit local address bus and a 16-bit local data bus, or
2. a 16-bit local address bus and a 16-bit local data bus.
c. How many bits are needed for the program counter and the instruction register?
1.4 Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus.
a. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”?
b. What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”?
c. What architectural features will allow this microprocessor to access a separate “I/O space”?
d. If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain.
1.5 Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock frequency supplied to the microprocessor? State any other assumptions you make and explain. Hint: Determine the number of bytes that can be transferred per bus cycle.
1.6 Consider a computer system that contains an I/O module controlling a simple keyboard/ printer Teletype. The following registers are contained in the CPU and connected directly to the system bus:
INPR: Input Register, 8 bits
OUTR: Output Register, 8 bits
FGI: Input Flag, 1 bit
FGO: Output Flag, 1 bit
IEN: Interrupt Enable, 1 bit
Keystroke input from the Teletype and output to the printer are controlled by the I/O module. The Teletype is able to encode an alphanumeric symbol to an 8-bit word and decode an 8-bit word into an alphanumeric symbol. The Input flag is set when an 8-bit word enters the input register from the Teletype. The Output flag is set when a word is printed.
a. Describe how the CPU, using the first four registers listed in this problem, can achieve I/O with the Teletype.
b. Describe how the function can be performed more efficiently by also employing IEN.
1.7 In virtually all systems that include DMA modules, DMA access to main memory is given higher priority than processor access to main memory. Why?

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