DIRECT DIGITAL SYNTHESIZERS ARE KNOWN FOR THEIR HIGHLY ACCURATE DIGITAL TUNING,LOW NOISE FIGURE, AND PHASE-CONTINUOUS FREQUENCY-HOPPING CAPABILITIES, WHICH MAKE THEM MORE ATTRACTIVE THAN ALTERNATIVE ANALOG FREQUENCY-SYNTHESIS SOLUTIONS.
Y
ou find DDSs (direct digital synthesizers) in applications such as radios,instrumentation,and radar systems.Though large and unpre-dictable spurious responses have troubled old de-signs,innovations have improved DDS perform-ance,and the worst-case spurs are now smaller and predictable.Careful frequency planning allows you to place the worst-case spurs outside the bandwidth of interest,so you can easily filter them.
Most DDS applications use only a fraction of their output spectrum and attenuate the remainder with external filters.The bandwidth of interest is typi-cally from 0 Hz to about 40% of the sampling fre-quency.The sub-Nyquist limitation is due to the transition band of the external image-rejection fil-ter.Some applications can use the image band and eliminate an upconversion stage,but the reduced power in the image lowers the SNR.Image use also requires bandpass filtering rather than a lowpass fil-t
er.The DAC’s zero-order sample-and-hold imparts a Sinc (sin(x)/x) attenuation envelope to the funda-mental,images,and harmonics in the DDS spec-trum.
A DDS has four principal spur sources:the refer-ence clock,truncation in the phase accumulator,
gle-to-amplitude mapping errors,and DAC error terms,including nonlinearities and quantization noise (Figure 1).The spur frequencies’REFERENCE CLOCK
the DAC as its output.the reference clock directly impact those of put.clock also appear at the DAC out
put,The improvement,expressed in decibels,log(N),where N is the ratio of quencies.For example,ference in their phase-noise plots of 20 log(16)ϭ24dB (Figure 2).The DDS’s internal reference-clock path is the dominant contributor of phase noise from the DDS.
Modulating the clock amplitude generates spurs in its output spectrum.A 400-MHz RF carrier with 10% AM (amplitude modulation) by a 100-kHz sine-wave signal demonstrates the effect you see at the reference clock and 10.119-MHz DDS outputs (Figure 3).The figure ,which superimposes the ref-erence-clock and DAC-output spectra,shows the amplitude reduction in AM clock spurs at the DDS output.The attenuation calculation,20 log (400MHz/10.119 MHz),predicts a 32-dB improvement,although the plot shows more.The additional spur attenuation is due to the fact that the modulated sine wave of the reference-clock signal encounters a lim-iter or squaring circuit at the DDS input.The lim-iter stage converts the sine wave to a square wave,and the AM spurs are thus converted to PM (phase mod-ulation) spurs.The AM-to-PM conversion results in an additional attenuation of spurs that depends on the characteristics of the limiter circuit but is typi-cally on the order of Ϫ6 dB.
DDS design
design feature By David Brandon, Analog Devices
The quality of ways that are often recognizable.quency.Also,noise at the input of any circuit.cause jitter.PHASE TRUNCATION
accumulator.If 32 bits throughout,nificant power.tion of thesizer (Figure 4).word width.Each update of clock adds the value of lator output.ed into two sections,ed phase word,P ,mapper,and the discarded bits,cumulates,the truncated dulation spurs.quency resolution of T.Note,word and,therefore,sues.Conversely,a DDS drives a PLL,should be 3 or more bits
wider than the DAC resolu-tion suggests.
It’s unlikely that the Va
i that the system
calculates corresponds exactly to a DAC code,so the DDS selects the nearest code, resulting in a residual error.If the phase
truncated 带where
word has too few bits,the Va
i calculation
may skip over DAC codes (Figure 6).Conversely,retaining more bits in the
phase word reduces these errors (Figure
7).To guarantee that all DAC codes are
available to the phase-to-amplitude con-
verter,a good rule of thumb is to set the
phase word to a minimum of3 bits wider
than the DAC.The red trace in Figure 7
represents the amplitude error signal re-
sulting from the DAC’s finite resolution.
It indicates the difference between Va
i
and the actual DAC codes.A Fourier
transform of this time-domain plot
the spurious response that the ampli-tude-error signal causes (Figure 8).The plot includes no DAC-error effects.The DDS tuning word is 32 bits,the phase word is 19 bits,the reference clock is 100M samples/sec,and the DAC resolu-tion is 10 bits.The tuning word is 30002000H,which results in a carrier fre-quency of18.75021876 MHz.The stair-
step spectrum results from the ampli-
tude-error signal modulating the carrier.
The dominant,or worst-case,spurs are
offset approximately Ϯ700 kHz from the
carrier with this tuning word.Their lo-
cation depends on the tuning word and
the DDS architecture.Their power level
is below the DAC’s expected SNR,which
is a goal of the design.A DAC with
greater resolution would decrease the
magnitudes of these spurs.A similar
DDS implemented with an algorithmic
sine mapper instead of the ROM-based
structure produces a similar spectrum
(Figure 9).
1.Accurately measure and record the
reference-clock frequency,f
REF ,to a Ϯ1-
Hz tolerance.
2.Counting from the MSB of the tun-ing word,assert only the bth bit.The bth bit is defined as bthͧnϩ8;that is,if the DAC width is 10 bits,then set 18th bit or higher counting from the MSB.
3.Calculate the tuning-word frequen-
cy,f
C
,from f
REF
and the tuning word.
4.Use Equation 4to locate the fre-
quency region of the prominent spur
set to measure.N ote that the spacing
between these sets of spurs is two times
the tuning-word frequency.
5.Measure and record the frequency of
each individual spur in the worst-case set.
6.Individually divide the frequencies
of the worst-case spur set by the tuning
word.Round the results to the nearest
Figure 8
(cont’d on pg 83)

版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。