专利名称：3.5 transistor non-volatile memory cell using gate breakdown phenomena
发明人：John M. Callahan,Hemanshu T.
Vernenker,Michael D. Fliesler,Glen Arnold
Rosendale,Harry Shengwen
Luan,Zhongshang Liu
申请号：US11252461
申请日：20051018
公开号：US07173851B1
公开日：
20070206
专利内容由知识产权出版社提供
truncate读专利附图：
摘要：A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.
申请人：John M. Callahan,Hemanshu T. Vernenker,Michael D. Fliesler,Glen Arnold Rosendale,Harry Shengwen Luan,Zhongshang Liu
地址：San Ramon CA US,Santa Clara CA US,Santa Cruz CA US,Palo Alto CA US,Saratoga CA US,Plano TX US
国籍：US,US,US,US,US,US
代理机构：Perkins Coie LLP
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