SV之数据类型
⽬录
SV是对verilog的扩展，verilog中⼀般使⽤reg和wire两种数据类型，下表显⽰了SV的扩展类型：
下表为数据类型的四种状态：
四值数据类型只有wire、reg、integer 、logic、time五种，其余的都是⼆值数据类型，其中logic是SV新加的类型！然后SV中⽤real和realtime代替了C中的double来表⽰浮点数.常⽤的数据类型⼀般只有logic和bit、time、wire、reg⼏种.
下⾯看⼀个SV显⽰浮点数和⼩数的例⼦：
module tb;
real pi; // real类型代替了double
real freq;
initial begin
pi = 3.14; // Store floating point number
freq = 1e6; // Store exponential number
$display ("Value of pi = %f", pi);
$display ("Value of pi = %0.3f", pi);
$display ("Value of freq = %0d", freq);
end
endmodule
module assignment_operator ();
logic a;
reg b;
bit c;
initial begin
a=1'bx;
b=1'b0;
c=1'bz;//对⼆值类型赋不定值，输出的是其默认值0
$display("a=%b",a);
$display("b=%b",b);
$display("c=%b",c);
end
endmodule
SV中的字符串
string myMessage2 = "Hello World"; // Uses "string" data type
structures 结构体
typedef struct {//定义⼀个名为s_money的结构体
int coins;
real dollars;
} s_money;
// Create a structure variable of type s_money
s_money wallet;//创建⼀个结构体变量c++string类型
wallet = '{5, 19.75}; // Assign direct values to a structure variable
wallet = '{coins:5, dollars:19.75}; // Assign values using member names
wallet = '{default:0}; // Assign all elements of structure to 0
wallet = s_money'{int:1, dollars:2}; // Assign default values to all members of that type
// Create a structure that can hold 3 variables and initialize them with 1
struct {
int A, B, C;
} ABC = '{3{1}}; // A = B = C = 1 初始化结构体元素
// Assigning an array of structures
s_money purse [1:0] = '{'{2, 4.25}, '{7,1.5}};//创建⼀个结构体数组
logic and bit
本节我们将关注4值和2值逻辑类型，以及SV中新添加的logic和bit类型.
4-state data types
4值逻辑类型的4个值分别是0、1、X或x、Z或z（默认为X）.传统的verilog中的reg只能在always、initial等过程块中赋值，wire只能使⽤连续赋值，⽽SV引⼊的logic类型既可以在过程块中赋值，也可以使⽤连续赋值 。注意，logic类型只能有⼀个驱动，多个驱动的数据要定义为线⽹类型wire。
module tb;
logic [3:0] my_data; // Declare a 4-bit logic type variable
logic en; // Declare a 1-bit logic type variable
initial begin
$display ("my_data=0x%0h en=%0b", my_data, en); //
my_data = 4'hB; // logic datatype can be driven in initial/always blocks
$display ("my_data=0x%0h en=%0b", my_data, en);
#1;
$display ("my_data=0x%0h en=%0b", my_data, en);
end
assign en = my_data[0]; // logic datatype can also be driven via assign statements
endmodule
logic类型的默认值是X，所以输出如下：
2-state data types
在很多情况下，SV中并不需要⽤到变量的4个状态，例如数组长度，因此SV引⼊了⼆值逻辑状态变量类型bit。bit类型的状态要么是0要么是1，默认为0.
module tb;
bit var_a; // Declare a 1 bit variable of type "bit"
bit [3:0] var_b; // Declare a 4 bit variable of type "bit"
logic [3:0] x_val; // Declare a 4 bit variable of type "logic"
initial begin
// ⼆值逻辑的默认值为0
$display ("Initial value var_a=%0b var_b=0x%0h", var_a, var_b);
// Assign new values and display the variable to see that it gets the new values
var_a = 1;
var_b = 4'hF;
$display ("New values var_a=%0b var_b=0x%0h", var_a, var_b);
// If a "bit" type variable is assigned with a value greater than it can hold
// the left most bits are truncated. In this case, var_b can hold only 4 bits
// and hence 'h481 gets truncated leaving var_b with only 'ha;
var_b = 16'h481a;//var_b的位宽为4，所以会将左边的位数截断，只保留后4位
$display ("Truncated value: var_b=0x%0h", var_b);
// If a logic type or any 4-state variable assigns its value to a "bit" type
// variable, then X and Z get converted to zero
var_b = 4'b01zx;//如果将logic类型赋给bit类型，logic中的X和Z都会转换为0
$display ("var_b = %b", var_b);
end
endmodule
结果：
注意，将4值逻辑类型转换为2值类型时，4值类型中的不定值X和⾼阻态Z会转换为0。
'integer' and 'byte'
integer
四状态32bits有符号整数类型，SV引⼊了其他三种有符号的整数类型，它们是双状态的，分别为shortint、int、longint，位宽分别为16/32/64.
module tb;
//这三种类型都为⼆值类型，且默认情况下均带符号
shortint var_a;
int var_b;
longint var_c;
initial begin
// Print initial values of the integer variables
$display ("Sizes var_a=%0d var_b=%0d var_c=%0d", $bits(var_a), $bits(var_b), $bits(var_c));
// Assign the maximum value for each of the variables
// MSB of each variable represents the sign bit and is set to 0
// Rest of the bit positions are filled with 1 and hence you
/
/ get the maximum value that these variables can hold
#1 var_a = 'h7FFF;
var_b = 'h7FFF_FFFF;//最⾼位为0，这⾥三个数都是该种数据类型的最⼤整数
var_c = 'h7FFF_FFFF_FFFF_FFFF;
// When added a 1, the sign changes to negative because this is a signed variable
#1 var_a += 1; // Value becomes 'h8000 => which is a rollover from + sign to - sign
var_b += 1; // Value becomes 'h8000_0000 => which is a rollover from + sign to - sign
var_c += 1;
end
// Start a monitor to print out values of each variables as they change
initial
$monitor ("var_a=%0d var_b=%0d var_c=%0d", var_a, var_b, var_c);
endmodule
$bits()⽅法将返回变量的位宽数.将最⼤整数加1后将变为最⼩负数，所以结果如下：
我们将上⾯的例⼦变量的定义强制加上unsigned修饰，结果会怎么样？
module tb;
// In this case, we are going to make it unsigned which means
// that MSB no longer holds the sign information and hence these
// variables can only store positive values
shortint unsigned var_a;
int unsigned var_b;
longint unsigned var_c;
initial begin
// Print initial values of the integer variables
$display ("Sizes var_a=%0d var_b=%0d var_c=%0d", $bits(var_a), $bits(var_b), $bits(var_c));
// Assign the maximum value for each of the variables
#1 var_a = 'hFFFF;
var_b = 'hFFFF_FFFF;
var_c = 'hFFFF_FFFF_FFFF_FFFF;
// When added a 1, value rolls over to 0
#1 var_a += 1; // Value becomes 'h0
var_b += 1; // Value becomes 'h0
var_c += 1;
end
// Start a monitor to print out values of each variables as they change
initial
$monitor ("var_a=%0d var_b=%0d var_c=%0d", var_a, var_b, var_c);
endmodule
加1后产⽣进位，所以3个变量的值都变为0，结果如下：
byte
双状态8bits有符号整数.
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