TPS65270
www.ti SLVSAX7A–AUGUST2011–REVISED DECEMBER2011
4.5-V TO16-V INPUT VOLTAGE,2-A/3-A OUTPUT CURRENT,
DUAL SYNCHRONOUS STEP-DOWN REGULATOR WITH
INTEGRATED MOSFET
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FEATURES
•Wide Input Supply Voltage Range•Available in24-Lead Thermally Enhanced
(4.5V-16V)HTSSOP(PWP)and QFN4-mm x4-mm(RGE)
Packages
•0.8V,±1%Accuracy Reference
•Up to2-A(Buck1)and3-A(Buck2)Maximum
APPLICATIONS
Continuous Output Loading Current
•DTV
bootstrapped•Low Power Pulse Skipping Mode to Achieve
•DSL Modems
High Light Load Efficiency
•Cable Modems
•Adjustable Switching Frequency
300kHz-1.4MHz Set by External Resistor•Set Top Boxes
•Dedicated Enable and Soft-Start for Each Buck•Car DVD Players
•Peak Current-Mode Control with Simple•Home Gateway and Access Point Networks Compensation Circuit•Wireless Routers
•Cycle-by-Cycle Over Current Protection
•180°Out-of-Phase Operation to Reduce Input
Capacitance and Power Supply Induced Noise
DESCRIPTION/ORDERING INFORMATION
The TPS65270is a monolithic dual synchronous buck regulator with wide operating input voltage that can operate in5-,9-,12-or15-V bus voltages and battery chemistries.The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application.
The TPS65270features a precision0.8-V reference and can produce output voltages up to15V.Each converter features enable pin that allows dedicated control each channel that provide flexibility for power sequencing. Soft-start time in each channel can be adjustable by choosing different external capacitors.
Constant frequency peak current mode control simplifies the compensation and provides fast transient response. Cycle-by-Cycle over current protection and hiccup mode operation limit MOSFET power dissipation in short circuit or over loading fault conditions.Low side reverse current protection also prevents excessive sinking current from damaging the converter.
The switching frequency of the converters can be set from300KHz to1.4MHz with an external resistor.Two converters have clock signal with180°out-of-phase so as to minimize the input filter requirements and alleviate EMI and input capacitor requirements.
TPS65270also features a light load pulse skipping mode(PSM).The PSM mode allows a power loss reduction on the input power supplied to the system at light loading in order to achieve light load high efficiency.
The TPS65270is available in a24-Lead thermally enhanced HTSSOP(PWP)package and24-pin QFN 4-mm x4-mm(RGE)package.
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.Copyright©2011,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
TPS65270
SLVSAX7A –AUGUST 2011–REVISED DECEMBER 2011
www.ti
This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL APPLICATION
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BUCK1
BUCK2
Note: Pin numbers in block diagram are for HTSSOP (PWP) 24-pin package.
TPS65270
www.ti
SLVSAX7A –AUGUST 2011–REVISED DECEMBER 2011
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION (1)
T A
PACKAGE (2)ORDERABLE PART NUMBER
TOP-SIDE MARKING
PWP (R-PDSO-G)TPS65270PWPR
TPS65270–40°C to 85°C RGE (S-PVQFN-N24)
TPS65270RGER or TPS65270RGET
TPS65270
(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI web site at www.ti .
(2)
Package drawings,thermal data,and symbolization are available at www.ti/packaging .
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LX1LX1GND GND GND GND LX2LX2VIN2BST2
BST1VIN1PWP PACKAGE (TOP VIEW)
Exposed pad must be soldered to PCB for optimal thermal performance.
G N D
G N D
G N D
BST1L X 1
FB1EN1L O W _P O M P 1SS2FB2EN2A G N D
V C C
BST2C O M P 2
SS1R O S C
VIN2VIN1LX1
G N D
L X 2
LX2RGE PACKAGE (TOP VIEW)
Exposed pad must be soldered to PCB for optimal thermal performance.
TPS65270
SLVSAX7A –AUGUST 2011–REVISED DECEMBER 2011
www.ti
PIN OUT
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TPS65270 www.ti SLVSAX7A–AUGUST2011–REVISED DECEMBER2011
TERMINAL FUNCTIONS
NO.NO.
NAME DESCRIPTION
(HTSSOP)(QFN)
Enable for Buck1.Logic high enables the Buck1;Logic low disables
Buck1.If pin is left open a weak internal pull-up to V5V will allow for
EN1116
automatic enable;For a delayed start-up add a small ceramic capacitor
from this pin to ground.
Feedback voltage for Buck1.Connect a resistor divider to set0.8V from FB1217
the output of the converter to ground.
Soft start input for Buck1.An internal5-µA charging current is sourcing to SS1318this pin.Connect a small ceramic capacitor to this pin to set the Buck1
soft start time.
Loop compensation pin for Buck1.Connect a series RC circuit to this pin COMP1419
to compensate the control loop of this converter.
Low power operation mode.With active high,Buck1and Buck2operate LOW_P520at pulse skipping mode at light load;active low forces both Buck1and
Buck2to PWM mode;this pin can’t be left open.
Internal6.5-V power supply bias.Connect a10-µF ceramic capacitor from VCC621
this pin to ground.
AGND722Analog ground.Connect all GND pins and power pad together.
Oscillator frequency setup.Connect a resistor to ground to set the
ROSC823
frequency of internal oscillator clock.
Loop compensation pin for Buck2.Connect a series RC circuit to this pin COMP2924
to compensate the control loop of this converter.
Soft start input for Buck2.An internal5-µA charging current is sourcing to SS2101this pin.Connect a small ceramic capacitor to this pin to set the Buck1
soft start time.
Feedback voltage for Buck2.Connect a resistor divider to set0.8V from FB2112
the output of the converter to ground.
Enable for Buck2.Logic high enables the Buck2.Logic low disables
Buck2.If pin is left open a weak internal pull-up to V5V will allow for
EN2123
automatic enable;For a delayed start-up add a small ceramic capacitor
from this pin to ground.
Bootstrapped power supply to high side floating gate driver in Buck2. BST2134Connect a47-nF ceramic capacitor from this pin to the switching node pin
LX2.
Input supply for Buck2.Connect a10-µF ceramic capacitor close to this VIN2145
pin.
LX215,166,7Switching node connecting to inductor for Buck2.
GND17,18,19,208,9,10,11Power ground for Buck1and Buck2.
LX121,2212,13Switching node connecting to inductor for Buck1.
Input supply for Buck1.Conne ct a10-µF ceramic capacitor close to this VIN12314
pin.
Bootstrapped power supply to high side floating gate driver in Buck1. BST12415Connect a47-nF ceramic capacitor from this pin to the switching node pin
LX1.
Must be soldered to PCB for optimal thermal performance.Have thermal Thermal Pad
vias on the PCB to enhance power dissipation.
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TPS65270
SLVSAX7A–AUGUST2011–REVISED DECEMBER2011www.ti
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range(unless otherwise noted)
Voltage range at VIN1,VIN2,LX1,LX2–0.3to16V
Voltage range at LX1,LX2(maximum withstand voltage transient<10ns)–1to16V
Voltage at BST1,BST2,referenced to LX1,LX2pin–0.3to7V
Voltage at VCC,EN1,EN2,COMP1,COMP2,LOW_P–0.3to7V
Voltage at SS1,SS2,FB1,FB2,ROSC–0.3to3.6V
Voltage at AGND,GND–0.3to0.3V
T J Operating virtual junction temperature range–40to125°C
T STG Storage temperature range–55to150°C (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratings
only,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range(unless otherwise noted)
MIN NOM MAX UNIT VIN Input operating voltage  4.516V
T J Junction temperature–4085°C
ELECTROSTATIC DISCHARGE(ESD)PROTECTION
MIN MAX UNIT Human body model(HBM)2000V Charge device model(CDM)500V
PACKAGE DISSIPATION RATINGS(1)(2)(3)
T A=25°C T A=55°C T A=85°C PACKAGEθJA(°C/W)θJC(°C/W)
POWER RATING(W)POWER RATING(W)POWER RATING(W) PWP32.610  3.07  2.15  1.23
RGE32.610  3.07  2.15  1.23
(1)This assumes a JEDEC JESD51-5standard board with thermal vias with High K profile-See Texas Instruments application report
(SLMA002)regarding thermal characteristics of the PowerPAD™package.
(2)This assumes junction to exposed PAD.
(3)Based on JEDEC51.5HIGH K environment measured on a76.2x114x.6-mm board with the following layer arrangement:
(a)Top layer:2Oz Cu,6.7%coverage
(b)Layer2:1Oz Cu,90%coverage
(c)Layer3:1Oz Cu,90%coverage
(d)Bottom layer:2Oz Cu,20%coverage
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