5.3 State Retention and Restoration Methods
5.3 状态保存和恢复方法
Given a power switching fabric and an isolation strategy, it is possible to power gate a
block of logic. But unless a retention strategy is employed, all state information is lost
when the block is powered down. To resume its operation on power up, the block
must either have its state restored from an external source or build up its state from
the reset condition. In either case, the time and power required can be significant.
有了电源开关装置和隔离策略，就可以对逻辑块使用门控电源。除非使用了状态保持策略，否则所有的状态信息都会在电源关闭的时候丢失。为了在上电的时候恢复操作，被关闭的块要么从外部源恢复它的状态，要么初始化所有的状态。这两种情况需要的时间和功率都相当大。
In many cases, an explicit retention strategy for saving and restoring state quickly and
efficiently can provide a much faster and power-efficient method of getting the block
fully functional after power up.
许多情况下，对于保存和恢复状态有一个明确清晰的状态保存策略，可以使模块上电后恢复功能更快，功耗更小。
How essential a retention strategy is depends on the subsystem characteristics. A Dig-
ital Signal Processing unit that is primarily data-flow driven may be able to start from
reset if it is supplied with new input data. However a peripheral or cached processor
typically has enough residual state that the amount of bus traffic required to reload
this state is excessive.
状态保持策略的必要性依赖于子系统的特性。DSP单元主要是数据流的处理，如果有新数据到来，重启它就可以了。而外设和处理机高速缓存则有大量的状态需要保存，如果使用总线来读入这些保存的状态，那么总线会变得很繁忙。
There are several methods for saving and restoring the internal state of a power gated
block:
• A software approach based on reading and writing registers
• A scan-based approach based on using scan chains to store state off chip
• A register-based approach that uses retention registers
有几种保存和恢复门控电源块内部状态的的方法
• 基于读写寄存器的软件的方法
• 基于扫描链的方法（使用扫描链将状态存储到片外）
• 使用状态保持寄存器
With the software approach, a processor in an always on block reads the registers of
the power gated block during the power shutdown sequence. This state information is
stored in the processor’s memory. During the power up sequence, the processor reads
its memory and writes the state back into the power gated block. This method has sev-
eral drawbacks:
• The bus traffic considerably slows the power down and power up sequences.
• Bus conflicts can make the save/restore times non-deterministic, making it harder
to decide when it is worthwhile shutting down the block.
• Software must be written and integrated into the system’s software for handling
power down and power up. This makes the software much less reusable and
requires a much more extensive knowledge of the hardware on the part of the
engineers writing the software.
使用基于软件的方法，使用一个总是加电的处理器在下电序列时读出门控电源模块中的寄存器，将状态信息存储到处理器的内存当中。在上电序列时读出状态信息恢复到门控电源模块当中。这种方法有几个缺点：
• 总线传输使得下电和上电变得非常慢。
• 总线冲突使得存储和恢复状态的时间不可预测，使得关闭电源的时间难以决策。
• 软件必须被整合到系统软件当中来处理上电和下电，使得软件变得难以重用，而且使得软件编写人员不得不了解额外的硬件知识。
For these reasons, we will focus on the other two approaches to retention, which make
the power sequencing much more transparent to the rest of the system.
基于这些因素，我们主要关注另外两种策略，它们使得上电下电顺序对于系统其他部分来说更加透明。
5.3.1 State Retention Using Scan Chains
5.3.1 使用扫描链保持状态
Scan chains that are implemented for manufacturing test can be re-used to perform
state retention with almost no incremental area overhead.
design翻译扫描链本来用于测试，我们用扫描链保存状态就可以几乎不需要额外的开销。
In this approach, a dedicated set of scan chains is used for the power gated block.
During the power down sequence, the scan registers are shifted as in scan testing, but
the outputs are routed to a memory. This memory can be on chip or off chip, but if on
chip it needs to be always powered on. During the power up sequence the scan chains
are loaded from the memory.
在这种策略中，一组专用的扫描链被用于门控电源模块。在下电时，扫描寄存器如同扫描测试时一样将输出移出，并且把输出数据保存到存储器中。内存可以使片上的也可以是片
外的，如果是片上的那么它需要一直加电。在上电时，扫描链从存储器中读出保存的状态。
Note that once state is scanned out to memory, the entire subsystem can be power
gated off. There is no need to keep an always on power region for retention registers.
如果状态被扫描出并保存到内存当中，那么整个子系统的电源可以被关闭。相对于使用状态保持寄存器策略来说，扫描链方式不需要有总是加电的区域。
From an RTL design perspective there are of course challenges. The most basic chal-
lenge is that scan flops are not inserted and connected up until synthesis – yet it is
necessary to code and debug the controller at the RTL level, before synthesis.
从RTL设计的角度来看，扫描链方式存在着必然的挑战。最基本的挑战是扫描链的插入和连接是在综合之后才进行的，这使得在综合之前，在RTL级设计时编写和调试控制器。

版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。