《功率因数校正开关电源的研究与设计》外文翻译
Switching Power Supply Design(开关电源设计)
CHAPTER 3
Half- and Full-Bridge
Converter Topologies
3.1 Introduction
Half-bridge and full-bridge topologies stress their transistors to a voltage equal to the DC input voltage not to twice this value, as do the push-pull, single-ended, and interleaved forward converter to pologies. Thus the bridge topologies are used mainly in offline converters where supply voltage would be more than the switching transistors could safely tolerate. Bridge topologies are almost always used where the normal AC input voltage is 220 V or higher, and frequently even for 120-V AC inputs.
An additional valuable feature of the bridge topologies is that primary leakage inductance spikes (Figures 2.1 and 2.10) are easily clamped to the DC supply bus and the energy stored in the leakage inductance is returned to the input instead of having to be dissipated in a resistive snub -ber element.
3.2 Half-Bridge Converter Topology
3.2.1 Basic Operation
Half-bridge converter topology is shown in Figure 3.1. Its major
advantage is that, like the double-ended forward converter, it subjects the “off” transistor to only V dc and not twice that value. Thus it is widely used in equipment intended for the European market, where the AC input voltage is 220 V. First consider the input rectifier and filter in Figure 3.1. It is used universally when the equipment is to work from either120-VACAmerican power or 220-V AC European power. The circuit always yields roughly
320-V rectified DC voltage, whether the input is 120 or
FIGURE 3.1 Half-bridge converter. One end of the power transformer primary is connected to the
junction of filter capacitors C1, C2 via a small DC locking capacitor Cb . The other end is connected to the junction of Q1, Q2, which turn “on” and “off” on alternate half cycles. With S1 in the closed position, the circuit is a voltage doubler ; in the open position, it is a full-wave rectifier. In either case, the rectified output is about 308 to 336 V dc.
220 V AC. It does this when switch S1 is set to the open position for
220-V AC input, or to the closed position for 120-V AC input. The S1 component is normally not a switch; more often it is a wire link that is either installed for 120 V AC, or not for 220 V AC.design翻译
With the switch in the open 220-V AC position the circuit is a full wave rectifier, with filter capacitors C1 and C2 in series. It produces a peak rectified DC voltage of about (1.41×220) −2 or 308 V. When the switch is in the closed 120-V AC position , the circuit acts as a voltage doubler. One half cycle of the input voltage when A is positive relative
to B, C1 is charged positively via D1 to a peak of (1.41 ×120) −1 or 168 V. On a half cycle when A is negative with respect to B, capacitor C2 is charged positively via D2 to 168 V. The total voltage across C1 and C2 in series is then 336 V. It can be seen in Figure 3.1 that with either transistor “on,” the “off” transistor is subjected to the maximum DC input voltage and not twice that value. Since the topology subjects the “off” transistor to only Vdc and not 2Vdc, there are many inexpensive bipolar and MOSFET transistors that can support the nominal 336 DC V plus 15% upper maximum of 386 V. Thus the equipment can be used with either 120- or 220-V AC line inputs by making a simple switch or linkage change.
Assuming a nominal rectified DC voltage of 336 V, the topology works as
follows: For the moment, ignore the small series blocking capacitor Cb . Assume the bottom end of Np is connected to the junction of C1 and C2. Then if the leakages in C1, C2 are assumed to be equal, that point will be at half the rectified DC voltage, about 168 V. It is generally good practice to place equal bleeder resistors across C1 and C2 to equalize their voltage drops. Now Q1 and Q2 conduct on alternate half cycles. When Q1 is “on” and Q2 “off” (Figure 3.1), the dot end of Np is 168 V positive with respect to its
no-dot end, and the “off” stress on Q2 is only 336 V. When Q2 is “on” and
Q1 “off,” the dot end of Np is 168 V negative with respect to its no-dot end and the emitter of Q1 is 336 V negative with respect to its collector.
This AC square-wave primary voltage produces full-wave square
Wave-shapes on all second-aries—exactly like the secondary voltages in the push-pull topology. The selection of secondary voltages and wire sizes and the output inductor and capacitor proceed exactly as for the push-pull circuit.
3.2.2 Half-Bridge Magnetics
3.2.2.1 Selecting Maximum “On”Time, Magnetic Core,
and Primary Turns
It can be seen in Figure 3.1, that if Q1 and Q2 are “on” simultaneously—even for a very short time—there is a short circuit across the supply voltage and the transistors will be destroyed. To make sure that this does not happen, the maximum Q1 or Q2 “on” time, which occurs at minimum DC supply voltage, will be set at 80% of a half period. The secondary turns will be chosen so that
the desired output voltages are obtained with an “on” time of no more than 0.8T/2. An “on”-time clamp will be provided to ensure that the “on” time can never be greater than 0.8T/2 under fault or transient conditions.
The core is selected from the tables in Chapter 7 mentioned earlier. These tables give maximum available output power as a function of operating frequency, peak flux density, core and iron areas, and coil current density.
With a core selected and its iron area known, the number of primary turns is calculated from Faraday’s law (Eq. 1.17) using the minimum primary voltage (Vdc/2) −1, and the maximum “on” time
of 0.8T/2. Here, the flux excursion dB in the equation is twice the desired peak flux density (1600 G below 50 kHz, or less at higher frequency), because the half-bridge core operates in the first and third quadrants of its hysteresis loop—unlike the forward converter (Section 2.3.9), which operates in the first quadrant only.
3.2.2.2 The Relation Between Input Voltage,
Primary Current, and Output Power
If we assume an efficiency of 80%, then
Pin = 1.25Po
The input power at minimum supply voltage is the product of minimum primary voltage and average primary current at minimum DC input. At minimum DC input, the maximum “on” time in each half period will be set at 0.8T/2 as discussed above, and the primary has two current pulses of width

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