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IT6604/IT6605 Register Table V1.03
Term:
RO: Read Only W/R: Read/Write
Reg Offset Reg_Name W/R
Bits Status Defau lt Description 0x00 VID_L RO 7:0  0x00 0x01 Backup_reg2 WR 7:0 Reserved 0x00 0x02 DEVID_L RO 7:0  0x23Device ID (Low word) 0x03 DEVID_H RO 7:0  0x60Device ID (High word)  0x04 DevRev RO 7:0  0xa3Device Revision Number 7 REG_CDR_RST 0 1: reset CDR.
6 Reserved 0  5 REG_AUTO_CDR_RST 0 1: Auto reset CDR 4 REGRST 0 1: Software reset the clock domain include
control registers to default
3 Reserved(not used) 0  2 AUDRST 0 1: Software reset audio logic 1 VDORST 0 1: Software reset video logic 0x05 Rst_Ctrl W/R 0 SWRST 0 1: Software reset all logic
7 PWD_Ch2 0 1: Power down channel2
6 PWD_Ch1 0 1: Power down channel1 5 PWD_Ch0 0 1: Power down channel0 4 PWD_ACLK 0 1: Power down Audio clock domain  3 PWD_PCLK 0 1: Power down Pixel clock domain 2 PWD_APLL 0 1: Power down Audio PLL 1 PWD_RXPLL 0 1: Power down Pixel PLL 0x06 Pwd_Ctrl0 W/R 0 PWD_ALL 0 1: Power down all AFEs and Logic blocks
4 Sel_port 0 Select active port:
0: portA
1: portB (IT6605 only)
3 PWD_AFEall 0 1: Power down all AFEs 2 PWDC_ETC 0 1: Power down certain AFE blocks 1 PWDC_SRV 0 1: Power down AFE equalizer 0x07 Pwd_Ctrl1 W/R 0 EN_AutoPWD 0 1: Auto Power down whole chip when no
clock is detected
7 VIO_Slew    1
Video data Slew rate
Slew rate: 0:Fast ; 1:Slow
6:4 VIO_ST 001 VDATA Driving Strength
000:2mA ; 001:4mA; 010:6mA ; 011:8mA;
100:10mA;101:12mA; 110:14mA;111:16mA;
3 Vclk_Slew    1
VCLK Slew rate
Slew rate: 0:Fast ; 1:Slow
0x08 VIO_Ctrl W/R 2:0 Vclk_ST 011 VCLK Driving Strength
000:2mA ; 001:4mA; 010:6mA ; 011:8mA;
100:10mA;101:12mA; 110:14mA;111:16mA;
7 AIO_Slew    1 Audio data Slew rate
Slew rate: 0:Fast ; 1:Slow
0x09 AIO_Ctrl W/R 6:4 AIO_ST 001
Audio data Driving Strength 000:2mA ; 001:4mA; 010:6mA ; 011:8mA; 100:10mA;101:12mA;
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110:14mA;111:16mA; 3 Mclk_Slew    1 Audio clock Slew rate
Slew rate: 0:Fast ; 1:Slow 2:0 Mclk_ST
001 Audio Driving Strength
000:2mA ; 001:4mA; 010:6mA ; 011:8mA; 100:10mA;101:12mA; 110:14mA;111:16mA; 0x0A Reserved W/R  0x2A  0x0B Reserved W/R
0xA5 0x0C BIST_Ctrl W/R 0 ARAM_BIST_EN 0 Internal Audio FIFO BIST test circuits 0x0D BIST_Result1 RO
7 6:0 ARAM_bo_faultHQ ARAM_D6FaulStauHQ  Audio FIFO BIST status 0x0E Reserved
0x0F Block_Sel W/R 0 Block_ID
Register block select
0: block 0 is select for Reading and writing 1: block 1 is select for Reading and writing 7 RXPLL_LOCK
x 1: RX PLL is lock 6 RXCK_Speed x 1: RX clock is lower than 80Mhz  5 RXCK_V ALID x 1: Clock is valid 4 HDMI_MODE x 1: HDMI mode or DVI mode (value:0) 3 P1_PWR5V_DET x 1: Port-1 5V is detect 2 SCDT
x 1: Video Sync is stable 1 VCLK_DET x 1: Video clock is detect 0x10 Sys_state
RO 0 PWR5V_DET
x 1: Port-0 5V is detect
0x11 HDCP_Ctrl W/R 7 6 5 4 3 2 1 0 ExtROM
reserved reserved reserved
HDCP_RomDisWr HDCP_A0 reserved HDCP_en
0x891: select internal OTP as HDCP key ROM
1: Disable external ROM write function 1: Select 0x76 as DDC address.(default is 0x74)
1: Enable HDCP  0x12 HDCP_Status RO 7-4 3 2 1 0 reserved
HDCP_ADVCipher HDCP_EESS
HDCP_KeyRd_Fail_Flag Hdcp_on_Flag
Show the HDCP authentication stauts
0x13 Interrupt0 RO    5 4 3 2 1 0 VidMode_Chg
HDMIMode_Chg SCDTOFF SCDTON Pwr5VOff Pwr5V on
‘1’: Video mode change
‘1’: HDMI/DVI mode swap change ‘1’: Video stable is off ‘1’: Video stable is on ‘1’: Selected port 5V is off ‘1’: Selected port 5V is on  0x14 Interrupt1 RO 7 6 5 4 3 2 1 0 PktLeftMute
NewAudioPkt_Det  NewACPPkt_Det NewSPDPkt_Det NewMPEGPkt_Det NewA VIPkt_Det NoA VI_Rcv PktSetMute
‘1’: Left Mute Packet is received
‘1’: New Audio Packet detect ‘1’: New ACP Packet detect ‘1’: New SPD Packet detect ‘1’: New MPEG Packet detect ‘1’: New A VI Packet detect ‘1’: No A VI Packet is received ‘1’: Set Mute Packet is received 0x15 Interrupt2 RO    5 4 3 2 1 0 ROMFault
AutoAudMute AudFIFOErr ECCERR Auth_done Auth_start
‘1’: ROM access Fault Flag
‘1’: Audio Auto Mute Flag ‘1’: Audio FIFO error Flag ‘1’: EDD error Flag
‘1’: Authentication Done Flag ‘1’: Authentication Start Flag
0x16 Interrupt_MASK0 W/R 5:0
0x3F Mask of interrupts defined in reg0x13
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1: The Interrupt is effective 0: The Interrupt is ineffective
0x17 Interrupt_MASK1 W/R 7:0  0x00Mask of interrupts defined in reg0x14
1: The Interrupt is effective 0: The Interrupt is ineffective
0x18 Interrupt_MASK2 W/R 7 Clr_HDCP_int
0 1:Clear interrupts generated by HDCP
authenticate start and done
5:0
0x00Mask of interrupts defined in reg0x15
1: The Interrupt is effective 0: The Interrupt is ineffective
1:Clear interrupts generated by HDCP signals 7 Clr_SetMute_int
0 1:Clear interrupts generated by set mute
packet  6 Clr_LeftMute_int 0 1:Clear interrupts generated by left mute
packet 5 IntrOutType    1 Interrupt pin output type
1:open drain 0:push pull 4 IntPol    1 Interrupt pin output polarity
1:low active 0:high active 3 Clr_Audio_int 0 1:Clear interrupts generated by Audio FIFO
error 2 Clr_ECC_int 0 1:Clear interrupts generated by ECC error 1 Clr_Pkt_int  0 1:Clear interrupts generated by Packet
signals  0x19 Interrupt_ctr
W/R 0 Clr_Mode_int
0 1:Clear interrupts generated by mode
change 7 reserved
0  6 reserved 0  5 reserved 0  4 Timeout_en
1 1:auto timeout when no DE detected
3 reserved 0  2 SelDebugHL
1 1:For Debug signals selecting  1 Vsync_Out_pol
0 Vsync output polarity 0: Negitave 1: Positive
0x1A Misc_ctrl
W/R 0 Hsync_Out_pol
0 Hsync output polarity 0: Negitave 1: Positive 7 Reserve
0 Reserve
6 chSyncpol
Video output data configuration, refer the datasheet and programming guide. 1: output sync signal polarity from Reg1A[1:0]
0: output sync signal polarity as the input. 5 Swap_O16b 0 1: when output 16-bit video data format, the other 8 bits will be forced to low
4 Swap_Ch422 0 Channel Swap used in YUV422 mode. 0:Cr/Cb assigned to Data[23:16] 1:Cr/Cb assigned to Data[7:0]
3 Swap_OutRB 0 1: swap output channel 0 and channel 2 2 Swap_ML 0 1: swap output direction(MSB/LSB) 1 Swap_Pol 0 1: swap input data polarity
0x1B Video_map
W/R 0
Swap_RB
1: swap input channel 0 and channel 2
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7
DNFreeGo 0 ‘1’: Dither Noise Pattern Select  6 SyncEmb 0 ‘1’: Sync Embedded output  5 EN_Dither 0 ‘1’: Enable dither function
4 EnUdFilt 0 ‘1’: Enable color up/down filter 3 OutDDR 0 ‘1’: Double data rate output 2 2x656CLK 0 ‘1’: CCIR656
5 output
1 656FFRst 0 ‘1’: CCIR656 Output FIFO reset 0x1C Video_Ctrl1
W/R 0 EnA VMuteRst
‘1’: Enable Output FIFO reset when A VMUTE is set.
0x1D Vclk_Ctrl
W/R    5 4 3:2  1:0 Vclkb_inv
Vclk_inv VclkbDly
VclkDly
0x30‘1’: Invert internal video clock phase
‘1’: Invert video output clock phase Fine tune internal video clock delay (1ns for 1 step)
Fine tune video output clock delay. (1ns for 1 step)
0x1E I2CIO_Ctrl
W/R 7  6  5:4  3:2  1:0
DSda_Slew
DDCSda_Slew
RomI2C_ST
DataI2C_ST
DDC_ST 0xDA Slew rate of command I2C pins:
0:Fast ; 1:Slow
Slew rate of HDCP I2C pins: 0:Fast ; 1:Slow
Current strength of ROM I2C pins:  00:4mA ; 01:8mA ; 10:12mA;11:16mA;
Current strength of command I2C pins: 00:4mA ; 01:8mA ; 10:12mA;11:16mA;
Current strength of HDCP I2C pins:  00:4mA ; 01:8mA ; 10:12mA;11:16mA; 0x1F RegPktFlag_ctrl W/R 4 3 2 1 0 ACP
SPD Audio MPEG A VI
0 0 0 0 0 0: interrupt only when first receiving or a new value is updated 1: interrupt each time a packet is received 7 VDGatting
0 Enable output data gating to zero when no
Video display. 6 VDIOLDisable 0 Disable video low bits data(D3~D0) 5 EN_TriVDIO 0 1: Enable Tristate Video Data Only
0: Tristate Video Data with Video Sync 4 ForceColMod 0 0: Input color mode auto detect
1: Force input color mode as bit[3:2] setting 3:2 ColMod_Set 00 Input color mode set
00: RGB mode 01: YUV422 mode 10: YUV444 mode
0x20 CSC_CTRL W/R 1:0 CSCSel
00 00: no color space change (bypass)
10: RGB to YUV 11: YUV to RGB
0x21 CSC_YOFF
W/R 7:0  0x10Color Space conversion parameters
matrix tables, refer the programming guide Y blank level 0x22 CSC_COFF W/R 7:0  0x80  C blank level 0x23 CSC_RGBOFF W/R 7:0  0x00R/G/B blank level
0x24 CSC_MTX11_L W/R 7:0  0xb2Color space conversion Matrix 0x25 CSC_MTX11_H W/R 5:0  0x04Color space conversion Matrix 0x26 CSC_MTX12_L W/R 7:0  0x64Color space conversion Matr
ix 0x27 CSC_MTX12_H W/R 5:0  0x02Color space conversion Matrix 0x28 CSC_MTX13_L W/R 7:0  0xE9Color space conversion Matrix 0x29 CSC_MTX13_H
W/R 5:0
0x00Color space conversion Matrix
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0x2A CSC_MTX21_L W/R 7:0
0x93
Color space conversion Matrix 0x2B CSC_MTX21_H W/R 5:0  0x1c Color space conversion Matrix 0x2C CSC_MTX22_L W/R 7:0  0x16Color space conversion Matrix 0x2D CSC_MTX22_H W/R 5:0  0x04Color space conversion Matrix 0x2E CSC_MTX23_L W/R 7:0  0x56Color space conversion Matrix 0x2F CSC_MTX23_H W/R 5:0  0x1F Color space conversion Matrix 0x30 CSC_MTX31_L W/R 7:0  0x49Color space conversion Matrix 0x31 CSC_MTX31_H W/R 5:0  0x1D Color space conversion Matrix 0x32 CSC_MTX32_L W/R 7:0  0x9f Color space conversion Matrix 0x33 CSC_MTX32_H W/R 5:0  0x1E Color space conversion Matrix 0x34 CSC_MTX33_L W/R 7:0  0x16Color space conversion Matrix 0x35 CSC_MTX33_H W/R 5:0  0x04Color space conversion Matrix 0x3B Deskew Setting
7:0 Deskew setting, suggestion
value is 0x40.
0x00Suggest Initial Value: 0x40
reserve W/R 7
reserve W/R 6  0
reserve W/R 5  0
reserve W/R 4  0
reserve W/R 3  0  DE_Bypass R/W 2 DE Bypass
0 0: DE regenerated
1: DE bypassed from TMDS input. reserve W/R 1  0
0x3C reserve W/R 0  0
W/R 7:6 OutColMod
10 Output color mode
00: RGB  01:YUV422 10:YUV444  reserved 00    reserved 00  0x3D PG_CTRL2  reserved
00  0x56 CDR Setting  0 CDR setting 0 should set as ‘1’ 0x58 Vid_mode RO    3 2 1 0 PxVideoStable
vidfield
vidinterlacemode VidModeChg
Indicate if video signal is stable
Video field number in interlaced mode Indicate video is in interlaced mode Indicate if a video mode change occurs 0x59 Vid_HTotal_L RO 7:0  The total pixel count of a line [7:0] 0x5A Vid_HTotal_H RO 7:4 3:0 Vid_HAct[11:8]
Vid_Htotal[11:8]
The active pixel count of a line[11:8]
The total pixel count of a line [11:8] 0x5B Vid_HAct_L RO 7:4 Vid_HAct[7:0]
The active pixel count of a line[7:0] 0x5C Vid_Hsync_Wid_L RO 7:4 Vid_Hsync_Wid[7:0]  The width of Hsync [7:0] 0x5D Vid_HSync_Wid_H RO 7:4 3:0 Vid_H_Ft_Porch[11:8]
Vid_Hsync_Wid[11:8]  The width of Hsync front porch [11:8]
The width of Hsync [11:8] 0x5E Vid_H_Ft_Porch_L
RO 7:0 Vid_H_Ft_Porch[7:0]
The width of Hsync front porch [7:0]
0x5F Vid_VTotal_L RO 7:0 Vid_VTotal[7:0]  The total line count of a field [7:0]
0x60 Vid_VTotal_H RO 7:4 3:0 Vid_Vact[11:8]
Vid_Vtotal[11:8]
The active line count of a field [11:8] The total line count of a field [11:8] 0x61 Vid_Vact_L RO 7:0 Vid_Vact[7:0]  The active line count of a field [7:0] 0x62 Vid_Vsync2DE RO 7:0 Video sync to DE[7:0]  The width of vsync back porch 0x63 Vid_V_Ft_Porch RO 7:0 Vid_V_Ft_Porch[7:0]  The width of vsync front porch
0x64 Vid_pixel_CNT RO 7:0  Count of crystal clock on each 128 pixels 0x65 Vid_input_st RO  7:4  3
Pix_rep
HDCP_DISABLE
Video input status 0000 : no repetition 0001: pixel sent 2 times 0011: pixel sent 4 times HDCP Disable:
1: HDCP Disabled
0: HDCP no activated or enabled

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