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IN-1
HOME CONTENTS
INDEX Index
A
all_clocks command 4-11annotated load 6-9arc
cell 5-28net 5-28arcs
case analysis and 2-70example of 2-71area
maximum
constraints for 1-15set maximum 1-20wire load models 3-13asynchronous clocks 4-61asynchronous logic constrain 2-92asynchronous paths maximum delay 2-11
optimization constraints 1-16,1-18set_max_delay command 1-16
set_min_delay command 1-16,1-18attributes
auto_disable_drc_net 4-33cell_degradation 2-27
default_wire_load 3-12,3-24drive strength constraints 2-5
fix_hold 2-14,4-35max_area 2-15
max_capacitance 1-9max_dynamic_power 1-3max_fanout 2-17design rule 1-8
max_leakage_power 1-3max_time_borrow 2-91max_transition 1-5min_capacitance 1-10remove
driving cell 5-14
set_auto_disable_drc_net 2-41wire_load_from_area 3-23
auto_disable_drc_net attribute 4-33auto_wire_load_selection variable 3-23automatic timing loop breaking 5-29
commands that can clear consistency table remove_disable_timing 5-30set_case_analysis 5-31set_disable_timing 5-30
commands that can write out consistency
table
write -format db 5-31write_script 5-31commands that initiate check_timing 5-30compile 5-30
report_disable_timing 5-30
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IN-2
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CONTENTS INDEX report_timing 5-30update_timing 5-30
B
back-annotation
post-layout net load 5-31
back-annotation expected delay approximation
4-31
balanced_tree (interconnect model)tree_types 3-6
best_case_tree (interconnect model)tree_types 3-6boundary conditions subdesign 6-6
C
calculations, characterize command 6-9capacitance
calculating 2-24control indirectly 1-9limit directly 2-24maximum 1-8,2-24control directly 1-9frequency-based 2-25minimum 1-10port 5-14
wire load models 3-13case analysis arcs and 2-70example of 2-71command syntax 2-73complex cells and example of 2-72
example methodology 2-81multiplexer and example of 2-73remove 2-73
report command 2-74example output 2-75
report disable timing command
example output 2-76sequential cells and 2-71using 2-70
case_analysis_log_file variable 2-77,2-78cell arc 5-28
cell degradation 1-11specifying 2-27cell name
path endpoint 2-9
cell_degradation attribute 2-27characterize
subdesign port signal interfaces 6-13combinational design 6-14sequential design 6-16subdesigns 6-3
characterize command 5-9,6-6,6-8calculations 6-9limitations 6-7check design 2-6
check_design command 2-6checks
clock gating
enable and disable 4-44setup and hold times 4-38hold 2-47setup 2-47violation
for maximum delay 2-11clock
asynchronous 4-58,4-61create 4-5,4-35
create generated 4-47cycle time 4-6derive 4-35divided 4-44edge 4-6
exclusive 4-58expansion 4-60gated clock
definition 4-38
enable and disable timing checks 4-44
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IN-3
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CONTENTS INDEX perform timing checks 4-38generated create 4-46
create divide-by-24-47create divide-by-34-48remove 4-56selecting 4-55
shifting the edges 4-50ideal 4-4,4-30latency 4-22
list all in design 4-11
multiple clock relationships 4-58
multiple clocks per register, specifying 4-57network 4-13
nonsingle-cycle behavior 4-1period 4-6
propagated 4-4,4-30remove 4-10select 4-55source 4-6identify 4-6
synchronous 4-58,4-59
synchronous path, constrain 4-7transition values, see 4-30tree 4-13
two-phase 5-19uncertainty model 4-16virtual 4-4waveform 4-6clock gating checks 4-38examples 4-43
command syntax 4-40definition 4-38
enable and disable timing checks 4-44perform timing checks 4-38timing violations checks 4-38clock information, report 4-12clock latency 4-14
minimum and maximum timing 4-26setting 4-21
clock network 4-13inverting 4-13latency 4-14
negative unate 4-66
non-unate 4-53,4-66,4-67
propagating clock paths 4-53,4-67positive unate 4-66preserving 4-33
specifying effects 4-13synthesize 4-13transition 4-14uncertainty 4-14clock network latency defined 4-22
multiple clocks per register 4-23clock path
non-unate 4-66clock pulse 4-6clock sense 4-66clock skew
characterize command 6-8
clock source latency, defined 4-22clock transition 4-14clock trees
automatically disabling DRC fixing 2-41clock uncertainty 4-14
interclock uncertainty 4-16setting 4-15
simple clock uncertainty 4-16clock, list of
commands 4-84
clock-based maximum transition,specifying
2-17
clocked scan
D latch equivalents 5-40definition 5-38clocks
create_clock command 1-16different cycle time 2-46multifrequency 2-46single-phase
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IN-4
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INDEX example 2-45virtual 6-20commands
all_clocks 4-11
characterize 5-9,6-6,6-8calculations 6-9check_design 2-6constraint, listed 2-95
create_clock 1-16,2-95,4-5,4-57create_generated_clock 4-46,4-47derive_clocks 4-35
derive_timing_constraints 2-5get_generated_clocks 4-55get_nets 2-38
get_path_groups 2-11get_pins 2-38get_ports 2-39
group_path 2-12,2-66,2-95max_dynamic_power 1-3max_leakage_power 1-3path-based listed 2-8read_sdf 4-31
remove_attribute 2-18,2-37,5-27remove_clock 4-10
remove_clock_gating_check 4-40remove_clock_groups 4-65remove_clock_transition 4-30remove_constraint 2-95remove_data_check 4-81
remove_disable_clock_gating_check 4-44remove_driving_cell 5-12
remove_generated_clock 4-56remove_ideal_latency 2-40remove_ideal_net 2-37
remove_ideal_network 2-37remove_ideal_transition 2-40remove_isolate_ports 2-23remove_output_delay 5-24
remove_wire_load_min_block_size 3-21remove_wire_load_model 3-20
reference group
remove_wire_load_selection_group 3-22report_attribute 2-37
report_case_analysis 2-74report_clock 4-12
report_constraint 2-93report_design 5-29
report_group_path 2-10report_ideal_network 2-37report_isolate_ports 2-23report_lib 3-7
report_lib output example 3-29report_mode 2-84report_net 2-38
report_port 5-9,5-26
report_timing_requirements 2-10,2-60reset_mode 2-85
reset_path 2-54,2-66,2-68
set_auto_disable_drc_nets 2-41,2-42,4-33,4-34
set_case_analysis 2-70
set_cell_degradation 1-11,2-27set_clock_gating_check 4-38,4-40set_clock_groups 4-62set_clock_la
tency 4-22set_clock_transition 4-28set_clock_uncertainty 4-16set_cost_priority 1-21set_critical_range 2-13set_data_check 4-77
set_disable_clock_gating_check 4-44set_disable_timing 5-27,5-28set_dont_touch_network 4-33set_drive 5-8,5-13
set_driving_cell 5-8,5-9,5-11set_equal 5-3
set_false_path 2-54,2-57,2-95set_fanout_load 1-8,2-18,5-17set_fix_hold 2-14,4-34
set_ideal_latency 2-29,2-39set_ideal_net 2-34
set_ideal_network 2-31,2-34set_ideal_transition 2-29,2-39set_input_delay 1-16,5-18,5-20
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IN-5
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INDEX set_input_parasitics port 5-15
report_timing 5-15set_input_transition 5-12set_isolate_ports 2-19set_load net 5-15port 5-15
set_logic_dc 5-4
set_logic_one 2-70,5-6set_logic_zero 2-70,5-6
set_max_area 1-20,2-15,2-95
set_max_capacitance 1-9,2-24,2-95
set_max_delay 1-16,2-54,2-64,2-65,2-95set_max_fanout 1-8,2-17,2-95set_max_time_borrow 2-90,2-95set_max_transition 1-6,2-16,2-95set_min_capacitance 1-10,2-26,2-95set_min_delay 1-16,2-54,2-67,2-95set_mode 2-82
set_multicycle_path 2-54,2-59,2-64,4-1set_multicylce_path 2-95
set_operating_conditions 3-6,3-9set_opposite 5-3
set_output_delay 1-16,5-18,5-20,5-23set_port_fanout_number 5-17set_propagated_clock 4-35set_s
can_configuration 5-32set_timing_derate 3-10set_unconnected 5-7
set_wire_load_min_block_size 3-21
set_wire_load_mode 3-16,3-18,3-19,3-20set_wire_load_model 3-18,3-19set_wire_load_selection_group 3-21compile
subdesigns 6-3test-ready 5-31
compiler directives 2-5complex cells
case analysis and example of 2-72constant nets automatically disabling DRC fixing 2-41constrained pin (for data check)4-76constraints
boundary conditions 6-6commands, listed 2-95cost vector 1-21design rule 1-3
cell degradation 1-11maximum area 2-15
maximum capacitance 1-8,2-24maximum fanout 1-6,2-17
maximum transition time 1-5,2-16minimum capacitance 1-10,2-26determine goals 2-5embedding 2-5
extract
derive_timing_constraints command 2-5maximum area 1-15
maximum capacitance 1-8maximum fanout 1-6
minimum capacitance 1-10minimum delay 1-18optimization 1-14
maximum area 1-20maximum delay 1-16minimum delay 1-18timing 1-16priorities 1-21
set_cost_priority command 1-21remove 2-95setting 2-4timing
asynchronous 1-15synchronous 1-15transition time 1-5cost calculation
maximum area 1-20maximum delay 1-17minimum delay 1-19cost function 1-2
design rule constraints 1-2
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IN-6
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CONTENTS INDEX design rules 1-4equation 1-4
maximum delay equation 1-17optimization 1-15
optimization constraints 1-2cost vector, constraints 1-21costing
path logic constants setting 2-70
create_clock command 4-5
multiple clocks per register 4-57
multiple clocks per register,specifying 4-7create_generated_clock command 4-46
multiple clocks per register, specifying 4-56syntax 4-47
critical range value setting 2-13
D
D flip-flop
multiplexed flip-flop equivalents 5-35D latches
clocked-scan equivalents 5-40LSSD equivalents 5-42
multiplexed flip-flop equivalents 5-37data checks
clock domains 4-82nochange check 4-80removing 4-81
set_data_check command 4-77timing reports 4-80
data checks, defining 4-75dctcl command language get_generated_clocks 4-55
get_path_groups command 2-11default path group 2-11
default_wire_load attribute 3-12,3-24default_wire_load_mode attribute 3-16delay
derating 3-10
fall 4-39
input, set 5-20maximum 1-16
cost calculation 1-17
set_input_parasitics command 5-15minimum
set_input_parasitics command 5-15output ports in combinational design 2-64output, setting 5-22rise 4-39delay value remove 5-24
derive_clocks command 4-35
derive_timing_constraints command 2-5design
characterize 6-3
logical connections of ports 6-17check for problems 2-6determine constraints 2-5feedback loops break 5-27
interconnect model 3-4,3-8internal timing 5-27multifrequency 2-46operating conditions 3-2
operating conditions parameters 3-4smallest, determine 2-15design rule
constraints 1-3precedence 1-11
max_capacitance attribute 1-9max_fanout attribute 1-8max_transition attribute 1-5maximum fanout calculation 1-7
maximum transition time 1-5,2-16min_capacitance attribute 1-10priorities 1-11
set_cell_degradation command 1-11set_fanout_load command 1-8
set_max_capacitance command 1-9set_max_fanout command 1-8

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