Understanding Bus-Hold—A Feature of Cypress CPLDs
This application note covers the bus-hold feature of Cypress’s F LASH 370i™, Ultra37000™, and Ultra37000V™ families of complex programmable logic devices (CPLDs). Included is a discussion of the history behind the bus-hold feature and spe-cific details about Cypress’s implementation of bus-hold.
Introduction
The F LASH 370i, Ultra37000, and Ultra37000V families of CPLDs have a unique feature called bus-hold on all I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch con-nected to the pin that does not degrade the device’s perfor-mance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototypes as designers can route new signals to the device without cutting trace connections to V CC  or GND.
Why Bus Hold—A Brief History
T o fully understand the need for the bus-hold feature, a knowl-edge of the history behind bus-hold is essential. There are three configurations of device I/Os and dedicated inputs that have been historically used in CPLDs. These configurations are:
1.Inputs and I/Os that are unbiased by internal circuitry ,
2.Inputs and I/Os with internal pull-up resistors, and
3.Inputs and I/Os with internal bus-hold latches.
A detailed description of each of these configurations is given in the sections that follow.
Devices With Unbiased Inputs and I/Os
Many CPLDs on the market today have dedicated inputs and I/Os similar to those shown in Figure 1. These inputs and I/Os have no internal biasing circuitry and are therefore commonly referred to as “floating” when no other circuitry is actively driv-ing the inputs.
When the input to the CPLD is floating, oscillations can occur due to the potential of externally biasing the input buffer around its trip point. Due to the fact that the floating input is very high impeda
nce, noise injected from other components on the board can cause the input to move around the trip point of the input buffer as shown in Figure 2. Each time the input voltage transitions across the trip point of the input buffer, the input buffer will change state. The change in state can prop-agate completely through the device and cause outputs of the CPLD to switch. Switching the CPLD outputs creates more noise on the board, increases the switching noise on the float-ing input, and potentially creates device oscillation. This os-cillation can result in functional problems with the design as well as increase the power requirements of the CPLD.Due to the oscillation problems inherent with floating inputs,designers must ensure that the inputs to the CPLD are always properly biased. This requires all unused pins to be connect-ed to V CC  or GND. This hard-wired connection will require the designer to cut PCB traces to make any modifications to the design that requires the use of a previously unused pin. De-signs that have bus interfaces, or inputs that can be left float-ing by circuitry external to the device, must take care to bias the signal traces on the board to prevent this oscillation. This requires, at minimum, an external pull-up resistor to ensure that the input is biased to a voltage that is not near the trip point of the device.
ESD
Protection
Pin Feedback
Pull Down
Pull Up
Figure 1. Schematic of Dedicated Input and I/O with No Internal Biasing Circuitry
a. Input
b. I/O
Devices With Internal Pull-Up Resistors
As an improvement over the inputs and I/Os that are unbi-ased, an internal pull-up resistor is offered on some CPLDs as shown in Figure 3. This internal pull-up resistor eliminates the need for the designer to connect unused pins to V CC  or GND. Therefore, any unused pins can be utilized to imple-ment design changes without the need to cut the PCB traces to V CC  or GND.
However, the pull-up resistor does not eliminate the potential for device oscillation for designs that ha
ve bus interfaces or designs that have pins that can be left floating by external circuitry. When a bus signal transitions to three-state, the pre-vious state will determine if the potential for device oscilla-tions exist. If the previous state of the bus signal was HIGH,the pull-up resistor will simply maintain the current HIGH state. However, if the previous state of the bus signal was LOW, the pull-up resistor will slowly transition the input or I/O to V CC . This results in an input voltage that slowly transitions through the region near the trip point of the input buffer. In order to allow the pull-up resistor to be easily overpowered by external drivers of the input or I/O, the internal pull-up resis-tances are typically large (50K Ω to 100K Ω). The large resis-tance value results in a very slow slew rate of the input voltage during the time it transitions from LOW to HIGH. Since the input voltage passes through the region near the trip point very slowly, noise from other components can potentially cre-ate device oscillation. Figure 4 is an example of what the ac-tual input voltage waveform can look like during this transition.
Devices With Bus-Hold Latches
T o alleviate the condition where the pull-up resistor slowly transitions from LOW to HIGH, the bus-hold circuit, shown in Figure 5, is connected to each dedicated input and I/O. The circuit is a latch that will hold the existing state of the bus whenever the bus is three-stated, hence the name bus-hold.
By retaining the previous state of the bus, the input voltage can not transition across the trip point of the input buffer when the bus is three-stated.
The latch is simply two inverters that loop back to the input of the device. The output voltage of the bus-hold circuit is limited to an NMOS threshold voltage below V CC  to match the V OH characteristics of the output driver in the I/Os, except for the Ultra37000V devices. The bus-hold feature is available on all F LASH 370i, Ultra37000, and Ultra37000V devices.
Bus-Hold Electrical Specifications
T able 1 lists the electrical specifications of the bus-hold latch.I BHL  and I BHH  are the LOW and HIGH sustaining currents respectively. This specification indicates that the bus-hold latch will sink or source 75 µA and still maintain the current state. As a result of this specification, the bus-hold latch will contribute 75 µA to the existing I OL  and I OH  specifications.This additional current results in a very small percentage change of I OH  and I OL  since these specifications are typically –3.2 mA and 16 mA respectively .
V IN
t
V TRIP
Input buffer switches each time input voltage transitions through trip point.
Figure 2. Possible Floating Input Voltage Due to Noise Figure 3. Input and I/O with an Internal Pull-up Resistor
ESD
Protection
100K Ω
Pull Down
Pull Up
100K
degrade
Ω
Pin Feedback
a. Input
b. I/O
Figure 4. Slow Rise Time with Pull-up Resistor V IN t
V TRIP
V OH
Input buffer switching during transition
I BHLO and I BHHO are the LOW and HIGH overdrive currents respectively. In order to change the state of the bus-hold latch, an external driver must source I BHLO or sink I BHHO, depending on the state of the bus-hold latch. For example, if the current state of the bus-hold latch is HIGH, an external driver must sink 500 µA to change the state of the bus-hold latch to LOW. Another electrical specification that is affected by the bus-hold feature is I OZ. I OZ is defined to be the output leakage current when the CPLD I/O is in three-state. For CPLDs that do not have bus-hold, or any other internal biasing circuits, this specification is usually a constant value regardless of the input voltage t
hat appears on the device I/O. However, for devices with bus-hold, or any other internal biasing circuits, the I OZ specification must account for the additional current supplied by this biasing circuitry. Figure 6 shows the worst-case additional current that is present on each input or I/O that has the bus-hold feature. As the input voltage, Vin, transitions from one state to another, the bus-hold latch will source or sink the amount of current indicated on the graph. For more specific details about bus-hold electrical specifica-tions and the test conditions, see the appropriate device data sheet.
Bus-Hold and 3.3V I/Os
The F LASH370i and the Ultra37000 families of CPLDs can be configured to operate in both 3.3V and 5.0V systems. There are two power supply configurations that allow the I/Os to operate at 3.3V:
1.Both the F LASH370i and the Ultra37000 families of CPLDs
allow a 5.0V internal and 3.3V I/O power supply.
2.The Ultra37000V family of devices allow a
3.3V only power
supply operation.
5.0V Internal, 3.3V I/O Configuration
All devices in both the F LASH370i and the Ultra37000 families of CPLDs have two separate sets of supply pins: one set, V CCINT, for the internal operation and input buffers and anoth-er set, V CCIO, for I/O output drivers. The V CCINT pins must be connected to a 5.0V power supply. However, the V CCIO pins may be connected to either a 3.3V or 5.0V power supply, de-pending on the output requirements.
Regardless of whether or not the V CCIO supply voltage is con-nected to 3.3V, the bus-hold circuitry is connected to the V CCINT supply which is connected to a 5.0V power supply. Therefore, when the V CCIO supply is connected to a 3.3V power supply, the bus-hold latch will affect the V OH of the device when the I/O is in three-state. This effect on V OH is described by the V OHZ electrical specification in the device
Table 1.Bus-Hold Electrical Specifications
Param Description Min Max Unit
I BHL Input Bus-Hold LOW
Sustaining Current
+75µA
I BHH Input Bus-Hold HIGH
Sustaining Current
–75µA
I BHLO Input Bus-Hold LOW
Overdrive Current
+500µA
I BHHO Input Bus-Hold HIGH
Overdrive Current
–500µA
Pull Down
Pull Up
Pin Feedback Figure 5. Input and I/O with Bus-hold Latch
ESD
Protection
a. Input
b. I/O
IµA
I BHLO 500 µA
I BHHO–500 µA V IN
0V V TRIP of Input Buffer
3.3V
3.6V
–50 µA
–125 µA
4.0V
Figure 6. Bus-Hold IV Characteristics for 5.0V Internal
and 5.0V/3.3V I/O Supplies
data sheets. In general, if no I OH current is being supplied by
the device, the bus-hold latch will pull the output voltage up to approximately 4.0V as indicated in Figure 6. If this higher V OH
presents a problem for devices connected to this output, the
V OH can be lowered by simply placing a resistor to GND on the device I/O. If this resistor is sized such that an I OH of –50
µA is present, it will lower the output voltage to 3.6V as indi-cated in Figure 6. Lower V OH values, down to 3.3V, can be achieved by simply resizing the pull-down resistor in accor-
dance with the values on the graph in Figure 6. If the device
I/O is not in three-state, the output driver will actively supply
a 3.3V V OH.
3.3V Internal, 3.3V I/O Configuration
The Ultra37000V family of devices will allow a 3.3V-only pow-
er supply operation. For the 3.3V-only devices, the N-channel device in the output path of the bus-hold circuit is removed on both the inputs and I/Os as shown in Figure 7. Both the bus-hold latch and the I/O output driver are connected to the 3.3V power supply. Even though the bus-hold latch is con-nected to a 3.3V power supply, the I BHLO and I BHHO specs are the same as if the bus-hold latch were connected to a 5.0V power supply. The only difference is the V OH of the output driver and the bus-hold latch will be limited to 3.3V. Figure 8 is a graph of the worst-case bus-hold current for the 3.3V power supply option on the Ultra37000V family of devices.Bus-Hold and External Circuitry
The interface of devices with the bus-hold feature is different from devices that have internal pull-up resistors or to devices that have no internal biasing. Several specific differences in-clude how to properly size an external resistor to V CC and the fan-out effects of connecting multiple device inputs or I/Os to a signal in a bus. These differences are discussed in the ex-amples that follow. These examples assume that the devices are configured for 5.0V power supply operation; however, the same applies for 3.3V I/O power supply operation.
Proper External Resistor Sizing
Many designs require the use of an external pull-up resistor with a CPLD. An example is a design with a set of DIP switch-es that allow the user to configure the design according to their specific needs. Figure 9 shows an equivalent schematic of how the DIP switch could be connected. When the switch is closed, the pin on the CPLD is shorted to GND and when the switch is open, the pull-up resistor will pull the pin on the CPLD to V CC.
Several parameters must be known in order to properly size the pull-up resistor, R1, shown in Figure 9:
1.The bus-hold overdrive current, I BHLO.
2.The trip point of the bus-hold latch, V TRIP. This value is
always the same as the normal input buffer of the device.
For the F LASH370i, Ultra37000, and Ultra37000V devices, the input trip point is nominally 1.5V.
3.Worst case V CC, V CC MIN. For the commercial tempera-
ture range of the 5.0V F LASH370i and Ultra37000 families of CPLDs, V CC MIN is 4.75V.
Once these parameters are known, the proper pull-up resistor size can be determined by:
Which results in a pull-up resistance of:
Designers that have applications that require a pull-down re-sistor can use a similar method to determine the resistor sizing.
Connected to
Input and I/O
N-Channel device removed
Figure 7. 3.3V Bus-hold Latch
I µA
I BHLO 500 µA
I BHHO–500 µA V IN
0V V TRIP of Input Buffer
3.3V
Figure 8. Bus-Hold IV Characteristics for 3.3V Internal
and 3.3V I/O Supply
R1
Pin of CPLD
with Bus-Hold
DIP Switch
Figure 9. Example Design with DIP Switches
5.0V
R1
V CC MIN V TRIP
–
I BHLO
-----------------------------------------------
=
R1
4.75V  1.5V
–
500µA
----------------------------------  6.5KΩ
==
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use RC Power-up Circuits and Bus-hold
Another common circuit configuration that can be affected by the external pull-up resistor sizing is shown in Figure 10. This circuit configuration is often used as a power-up circuit for the CPLD and the system. In order to achieve the correct RC time constant for the circuit, the resistor size cannot be adjusted above the 6.5 K Ω calculated above. If a pull up resistor larger than 6.5 K Ω is used, the bus-hold latch will prevent the ca-pacitor from being charged to a voltage that is high enough to switch the bus-hold latch. Therefore, the circuit will never transition out of the powered down state.Fan-out Effects of Bus-hold Devices
Many designs that contain buses will also have multiple CPLDs connected to a signal in the bus. The designer should be aware of the additive nature of the overdrive currents of the bus-hold latch. For example, if a signal in a bus connects to three different CPLDs, each of which have a bus-hold latch,the overdrive current will be the maximum of (3 * I BHLO ) or (3*I BHHO ). For the specifications given in T able 1, the over-drive current for bus signals that connect to 3 CPLDs would increase to 1.5 mA. Figure 11 illustrates this example.
Summary
This application note provides the history behind the bus-hold feature and information on how to more effectively design with CPLDs that have bus-hold. The bus-hold feature is currently available on the F LASH 370i, Ultra37000, and Ultra37000V families of CPLDs.
The bus-hold feature of Cypress CPLDs can greatly improve the noise immunity of a design. By retaining the last state of the inputs, there is no opportunity for the floating input voltage to slowly transition through the trip point of the input buffer,thereby eliminating the potential for unwanted device oscilla-tions. The bus-hold feature also has the added benefit of al-lowing designers to leave unused input or I/O pins unconnect-ed. The bus-hold latch will bias the unconnected pins to a HIGH or a LOW state and keep the floating input voltage away from the trip point of the input buffer.
R1
Pin of CPLD
with Bus-Hold
C1
Figure 10. Typical Power-up Circuit for CPLDs 5.0V
F LASH 370i
or Ultra37000CPLD
F LASH 370i
or Ultra37000CPLD
F LASH 370i
or Ultra37000CPLD
500 µA 500 µA 500 µA
1.5 mA
Figure 11. Additive Nature of I BHLO  and I BHHO
I BHLO  or I BHHO
I BHLO  or I BHHO
I BHLO  or I BHHO

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