//接收端的解码模块（可综合）
//在信号接收的刚开始发送端发送的是10个1信号，
//即10个+M序列，所以我们在开始时每接收到一个信号做一次累加运算
//当出现正的高峰时则认为达到同步，进入同步解调过程（mainbody）。
//也就是从此每进入一个信号就进行相应的相乘相加，
//在解接收到31个信号后进行一次判断，大于0认为接收到1，小于0认为接收到0。
`timescale 1ns/1ns
module decoder( clk_31, //输入时钟
indata, //接收到的m序列
outdata, //解码以后的序列
rst,
en,
sum);
input clk_31,en,rst;
input [2:0] indata;
output [8:0] sum;
output outdata;
reg [8:0] i,j,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,
i11,i12,i13,i14,i15,i16,i17,i18,i19,
i20,i21,i22,i23,i24,i25,i26,i27,i28,i29,i30;
reg enable;
reg [30:0] flag; //叠加使能控制信号
reg [2:0] indata_buf;
reg [1:0] state;
reg outdata;
reg [8:0] sum;
wire [30:0] m;
parameter find_head =2'b01, //发送头信号111111110
main_body =2'b10; //到头信号之后的同步解码过程
assign m = 31'b 1010011000001110010001010111101;
//与发射端协调好的解调M序列
reg [8:0] sum0, //加法结果寄存器
sum1, //理论上我们是在每进入一个信号后就立即对已有的31个信号进行乘加运算，
sum2, //这是一个31位的加法，即使采用流水线算法也需要5个并行加法器。
sum3, //所以在实际实现的时候，我们为了提高处理速度，将这个运算转化为
sum4, //31个加法寄存器，将每次进来的信号与不同的31位M序列进行叠加，
sum5, //再存入不同的原有寄存器中，不同存器在寄进行了31次加法后进行一次判断，
sum6, //如果大于阈值则认为达到同步，进入同步判断状态（state<=main_body）
sum7,
sum8, //这组加法寄存器的初始值为50，进行31次乘法加法运算之后，选取的阈值为75
sum9,
sum10,
sum11,
sum12,
sum13,
sum14,
sum15,
sum16,
sum17,
sum18,
sum19,
sum20,
sum21,
sum22,
sum23,
sum24,
sum25,
sum26,
sum27,
sum28,
sum29,
sum30;
always@(posedge clk_31)
begin
if(!rst)
flag <=31'd1;
if(en)
begin
indata_buf <=indata;
case(i)
1: flag[1] <=1'b1;
2: flag[2] <=1'b1;
3: flag[3] <=1'b1;
4: flag[4] <=1'b1;
5: flag[5] <=1'b1;
6: flag[6] <=1'b1;
7: flag[7] <=1'b1;
8: flag[8] <=1'b1;
9: flag[9] <=1'b1;
10: flag[10]<=1'b1;
11: flag[11]<=1'b1;
12: flag[12]<=1'b1;
13: flag[13]<=1'b1;
14: flag[14]<=1'b1;
15: flag[15]<=1'b1;
16: flag[16]<=1'b1;
17: flag[17]<=1'b1;
18: flag[18]<=1'b1;
19: flag[19]<=1'b1;
20: flag[20]<=1'b1;
21: flag[21]<=1'b1;
22: flag[22]<=1'b1;
23: flag[23]<=1'b1;
24: flag[24]<=1'b1;
25: flag[25]<=1'b1;
26: flag[26]<=1'b1;
27: flag[27]<=1'b1;
28: flag[28]<=1'b1;
29: flag[29]<=1'b1;
30: flag[30]<=1'b1;
endcase
end
end
always@(posedge clk_31)
begin
if(!rst)
begin
i <=9'd0;
j <=9'd0;
sum0 <=9'd50;
sum1 <=9'd50;
sum2 <=9'd50;
sum3 <=9'd50;
sum4 <=9'd50;
sum5 <=9'd50;
sum6 <=9'd50;
sum7 <=9'd50;
sum8 <=9'd50;
sum9 <=9'd50;
sum10 <=9'd50;
sum11 <=9'd50;
sum12 <=9'd50;
sum13 <=9'd50;
sum14 <=9'd50;
sum15 <=9'd50;
sum16 <=9'd50;
sum17 <=9'd50;
sum18 <=9'd50;
sum19 <=9'd50;
sum20 <=9'd50;
sum21 <=9'd50;
sum22 <=9'd50;
sum23 <=9'd50;
sum24 <=9'd50;
sum25 <=9'd50;
sum26 <=9'd50;
sum27 <=9'd50;
sum28 <=9'd50;
sum29 <=9'd50;
sum30 <=9'd50;
sum <=9'd50;
enable <=1'b0;
state <=find_head;
end
else
if(en)
begin
case(state)
find_head:
begin
if(!enable)
enable <=1'b1;
else
begin
if(flag[0])
begin
i1 <=i;
if(indata[2]==m[i])
sum0 <=sum0+{((indata[2]^indata[1])||((indata[2]
&&indata[1])&&(!indata[0]))),indata[0]};
else
sum0 <=sum0-{((indata[2]^indata[1])||((indata[2]
&&indata[1])&&(!indata[0]))),indata[0]};
if(i==30)
begin
i <=9'd0;
if(sum0>=75)
begin
outdata <=1'b1;
state <=main_body;
end
else
state <=find_head;
end
else
i <=i+1;
end
if(flag[1])
begin
i2 <=i1;
if(indata[2]==m[i1])
sum1 <=sum1+{((indata[2]^indata[1])||((indata[2]
&&indata[1])&&(!indata[0]))),indata[0]};
else
sum1 <=sum1-{((indata[2]^indata[1])||((indata[2]
&&indata[1])&&(!indata[0]))),indata[0]};
if(i1==30)
begin
i1 <=9'd0;
if(sum1>=75)decoder
begin
outdata <=1'b1;
state <=main_body;
end
else
state <=find_head;
end
end
if(flag[2])
begin
i3 <=i2;
if(indata[2]==m[i2])
sum2 <=sum2+{((indata[2]^indata[1])||((indata[2]
&&indata[1])&&(!indata[0]))),indata[0]};
else
sum2 <=sum2-{((indata[2]^indata[1])||((indata[2]
&&indata[1])&&(!indata[0]))),indata[0]};
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