Together with the American National Standards Institute(ANSI),the Institute of ANSI
Electrical and Electronic Engineers(IEEE)has developed a standard set of logic IEEE
symbols.The most recent revision of the standard is ANSI/IEEE Std91-1984,
IEEE Standard Graphic Symbols for Logic Functions.It is compatible with
standard617of the International Electrotechnical Commission(IEC),and must
be used in all logic diagrams drawn for the U.S.Department of Defense.
A.1GENERAL DEFINITIONS
The IEEE standard supports the notion of bubble-to-bubble logic design with the
following definitions:
•An internal logic state is a logic state assumed to exist inside a symbol internal logic state outline at an input or an output.
•An external logic state is a logic state assumed to exist outside a symbol external logic state outline either(1)on an input line prior to any external qualifying symbol at
that input,or(2)on an output line beyond any external qualifying symbol
at that output.
791
792IEEE STANDARD SYMBOLS APP.A
A qualifying symbol is graphics or text added to the basic outline of a device’s qualifying symbol
logic symbol to describe the physical or logical characteristics of the device.The
“external qualifying symbol”mentioned above is typically an inversion bubble,
which denotes a“negated”input or output,for which the external0-state corre-
sponds to the internal1-state.This concept is illustrated in Figure A–1.When
the standard says that a signal is in its internal1-state,we would say that the internal1-state
signal is asserted.Likewise,when the standard says that a signal is in its internal internal0-state
0-state,we would say that the signal is negated.
Figure A–1
Internal and external logic states.
logic
states
logic
states
The IEEE standard provides two different types of symbols for logic gates. distinctive-shape
symbols One type,called distinctive-shape symbols,is what we’ve been using all along.
The other type,called rectangular-shape symbols,uses the same shape for all rectangular-shape
symbols the gates,along with an internal label to identify the type of gate.Figure A–2 compares the two types.According to the IEEE standard,“the distinctive-
shape symbol is not preferred.”Some people think this statement means that
rectangular-shape symbols are preferred.However,all the standard really says is
that it gives no preference to distinctive-shape symbols compared to rectangular-
shape symbols.On the other hand,since most digital designers,authors,and
computer-aided design systems prefer the distinctive-shape symbols,that’s what
we use in this book.
Before the promulgation of the IEEE standard,logic symbols for larger-scale logic elements were drawn in an ad hoc manner;the only standard rule
was to use rectangles with inputs on the left and outputs on the right.Although
the logic symbol might contain a short description of the ,“3–8
ANOTHER KIND OF BUBBLE In addition to the familiar bubble,the IEEE standard also allows an external, triangular“polarity symbol”to be used to specify active-low inputs and outputs, for which the external LOW level corresponds to the internal1-state.However, under a positive-logic convention,the bubble and the triangular polarity symbol are equivalent,so we use the more traditional bubble in this appendix.
Copyright©1994by John F.Wakerly Draft of July6,1999
SEC.A.2DECODERS
793
Figure A–2
Distinctive-and rectangular-shape logic symbols.
OR
NOR
INVERTER
BUFFER
decoder,”“2–1multiplexer”),it was usually necessary to refer to a separate table to determine the element’s logic function.However,the IEEE standard contains a rich set of concepts,such as bit group
ing,common control blocks,and dependency notation,that allow some or all of a larger-scale logic element’s function to be displayed in the symbol itself.We’ll introduce these concepts as appropriate as we cover the symbols for various categories of devices in the sections that follow.
A.2DECODERS
Chapter 5used “traditional”logic symbols for decoders and other MSI logic elements.Although traditional symbols show the active levels of the inputs and outputs,they do not indicate the logical function of the device—you already have to know what a 74x138or 74x139does when you read its symbol.
The IEEE standard for logic symbols,on the other hand,allows a decoder’s logic function to be displayed as part of the symbol,shown in Figure A–3.These symbols use several concepts of the standard:
•Internal qualifying symbols.Individual input and output signals may be internal qualifying symbol
labeled with qualifying symbols inside the logic-symbol outline to describe the signals’characteristics.In this book,we call such symbols qualifying qualifying label labels for short.•G
eneral qualifying symbols.The top of a logic symbol may contain an general qualifying symbol alphanumeric label to denote the general function performed by the device.Decoders and encoders (called coders )use the general qualifying symbol coder
X /Y to indicate the type of coding performed,where X is the input code
Copyright
©1994by John F.Wakerly
Draft of July 6,1999
794IEEE STANDARD SYMBOLS APP.A Figure A–3
IEEE standard symbols for de-coders:(a)74x138;(b)74x139.
(a)
(b)
and Y is the output code.For example,a3-to-8decoder may be labeled
BIN/1-OF-8.
•Internal values.Each input combination of a coder produces an“internal internal value
value”that is displayed by the coder’s outputs.The internal values for a
3-to-8decoder are0–7.
•Input weights.The inputs of a coder may have qualifying labels indicating input weight
the numerical weights associated with those inputs.In this case,the internal
value at any time is the sum of the weights of the asserted inputs.The input
weights for a3-to-8decoder are1,2,and4.
•Output values.Each output may have a qualifying label listing the internal output value
values that cause that output to be asserted.In a binary decoder,each output
is asserted for just one internal value.
•Enable input.An enable input has the qualifying label EN and permits enable input
action when asserted.When negated,an enable input imposes the exter-
nal high-impedance state on three-state outputs,and the negated state on
other outputs.The74x138and74x139have active-low outputs,which are
therefore1when the enable input is negated.
•Embedded and abutted elements.The outlines of individual logic elements embedded element
may be embedded or abutted to form a larger composite symbol.There abutted element
is at least one common logic connection when the dividing line between
two outlines is perpendicular to the direction of signalflow,as shown in
Figure A–4.For example,the74x138symbol has an embedded3-input
AND gate that drives the internal EN input.There is no connection between
the elements when the dividing line is in the direction of signalflow,as
decodershown in Figure A–5.For example,the74x139contains two separate2-
to-4decoders.
Copyright©1994by John F.Wakerly Draft of July6,1999
SEC.A.2DECODERS 795
Figure A–4
A composite symbol with one or more logic connections between its elements.
The ability to embed individual logic elements in a larger symbol is probably the most useful feature of the IEEE standard.For example,Figure A–6shows the symbol for a 3-to-8decoder with a different set of enable inputs than the 74x138.The fictitious 74x328decoder is enabled when pin 6is 0or both pins 74x328
4and 5are 1.
Figure A–5
A composite symbol with no
connection between its
elements.
Figure A–6
IEEE standard symbol for a fictitious decoder,the 74x328.
Copyright
©1994by John F.Wakerly
Draft of July 6,1999

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