程序一：3-8译码控制数码管显示
library ieee;
use ieee.std_logic_1164.all;
entity decoder3_8 is
port(
a,b,c:in std_logic;
h :out std_logic;
y :out std_logic_vector(7 downto 0);
X :out std_logic_vector(7 downto 0);
en :out std_logic_vector(7 downto 0));
end decoder3_8;
architecture fun of decoder3_8 is
signal indata:std_logic_vector(2 downto 0);
begin
h<='1';
indata<=c&b&a;
encoder:
process(indata)
begin
case indata is
when "000"=>y<="11111110";
when "001"=>y<="11111101";
when "010"=>y<="11111011";
when "011"=>y<="11110111";
when "100"=>y<="11101111";
when "101"=>y<="11011111";
when "110"=>y<="10111111";
when "111"=>y<="01111111";
when others=>y<="XXXXXXXX";
end case;
end process encoder;
process(indata)
begin
case indata is
when "000"=>X<="01000000";
when "001"=>X<="01111001";
when "010"=>X<="00100100";
when "011"=>X<="00110000";
when "100"=>X<="00011001";
decoderwhen "101"=>X<="00010010";
when "110"=>X<="00000010";
when "111"=>X<="01111000";
when others=>x<="XXXXXXXX";
end case;
end process; end fun;

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