Introduction
Thank you for designing with the Xilinx Zynq®-7000 All Programmable SoC (AP SoC) family of devices. Although Xilinx has made every effort to ensure the highest possible quality, the devices listed in Table 1 are subject to the limitations described in the following errata.
Devices
These errata apply to the devices shown in Table 1.Processor System (PS) Errata Details
This section provides a detailed description of each processor system issue known at the release time of this document, including applicable errata from third-party IP, which has been modified to reflect implementation in the devices listed in Table 1. Additional information for each issue is available in the associated answer record. For a disposition of each ARM Cortex-A9 errata, see Answer Record 55518.
APU
Under Very Rare Timing Circumstances, Transition Into Streaming Mode Might Create A Data Corruption
Answer Record 65545
Under very rare timing circumstances, a data corruption might occur on a dirty cache line that is evicted from the L1 Data Cache due to another cache line being entirely written. The erratum requires the following conditions: •The CPU contains a dirty line in its data cache.
•The CPU performs at least four full cache line writes, one of which is causing the eviction of the dirty line.•
Another CPU, or the ACP, is performing a read or write operation on the dirty line.
This is a third-party errata (ARM, Inc. 845369); this issue will not be fixed.
Zynq-7000 AP SoC Production Errata
EN247 (v1.11) May 22, 2017
Errata Notification
Table  1:Devices Affected by These Errata
Product Family Device
JTAG ID (Revision Code)
Packages
Speed Grades
Junction
Temperature Range
Zynq-7000
XC7Z007S    1 or later All
All
All
XC7Z012S 0 or later XC7Z014S    2 or later XC7Z010  1 or later XC7Z0150 or later XC7Z020  2 or later XC7Z030  1 or later XC7Z035  2 or later XC7Z045  2 or later XC7Z100
0 or later
Read Accesses To DBGPRSR And DBGOSLSR Can Generate An Unexpected Undefined Exception
Answer Record 47560
CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an unexpected UNDEF exception when DbgSwEnable = 0, even in privileged mode. In practice, these registers are not accessible when DbgSwEnable = 0. However, this is not expected to cause any significant issue because these accesses are mainly intended to be used as part of debug across power-down sequences, which is not a supported feature.
The work-around is to set the DbgSwEnable bit to 1 temporarily so that the DBGPRSR and DBGOSLSR registers can be accessed. Note, the Control/Status Word register in DAP can only be accessed through PS JTAG.
This is a third-party errata (ARM, Inc. 764319); this issue will not be fixed.
The High Priority For SO And Dev Reads Feature Can Cause QoS Issues To Cacheable Read Transactions
Answer Record 47561
When the "High Priority for SO and Dev reads" feature is enabled, the L2 cache controller gives a higher priority to Strongly Ordered (SO) and Device read requests than normal cacheable reads. When the controller receives a continuous flow of SO/Device reads, the activity can prevent L2 cache line fill requests from being forwarded to the memory.
A work-around is only necessary in systems that are able to issue a continuous flow of SO or Device reads. In such a case, the work-around is to disable the "High Priority for SO and Dev reads" feature. This is the default setting in the L2 Controller. This is a third-party errata (ARM, Inc.729815); this issue will not be fixed.
A Continuous Write Flow Can Stall A Read Targeting The Same Memory Area
Answer Record 47562
When a read (cacheable or not) with Normal Memory attributes is received by the L2 cache controller, hazard checking is performed on the read with the active writes in the store buffer. If an address match is detected, the read is stalled until the write completes. However, a continuous flow of writes can stall a read targeting the same memory area.
This issue does not lead to data corruption and normal software code is not expected to contain long write sequences. This is a third-party errata (ARM, Inc. 754670); this issue will not be fixed.
L2 Cache Controller Can Prefetch Across 4KB Boundary With Offset Set To 23
Answer Record 47563
When prefetch is enabled and the prefetch offset is equal to 23 (0x17), then the L2 cache controller prefetches across a 4KB address boundary. This can cause system issues because those cache line-fills can target a new 4KB page of memory space, regardless of page attribute settings in the L1 MMU.
The offset values for the prefetch unit can be set from 0 to 31, but to avoid prefetching across the 4KB boundary, it must never be set to 23. The default value is 0 and enables the next cache line to be prefetched.
This is a third-party errata (ARM, Inc. 765569); this issue will not be fixed.
PLD Instructions Might Allocate Even In A Disabled Data Cache
Answer Record 47584
PLD instructions prefetch and allocate any data marked as Write-Back (either Write-Allocate or Non-Write-Allocate, Shared or Non-Shared), regardless of the processor configuration settings, including the Data Cache Enable bit value. This can create data consistency issues. This issue does not occur if the data cache is enabled.
The work-around requires software to set a bit in an undocumented Control register. Setting this bit causes all PLD instructions to be treated as NOPs.
This is a third-party errata (ARM, Inc. 771221); this issue will not be fixed.
Visibility Of Debug Enable Access Rights To Enable/Disable Tracing Is Not Ensured By An ISB Instruction
Answer Record 47585
Although visibility is correctly achieved for all debug-related features, the ISB instruction is not sufficient to make the Authentication Status Register changes visible to the trace flow. As a consequence, the trace stops with the current waypoint up to the next exception entry or return, or to the next serial branch, even when an ISB is executed.
To work around the issue, the ISB instruction must be replaced by one of the events causing the change to be visible. In particular, replacing the ISB by a MOVS PC to the next instruction achieves the correct functionality.
This is a third-party errata (ARM, Inc. 771224); this issue will not be fixed.
Speculative Cacheable Reads To Aborting Memory Regions Clear The Internal Exclusive Monitor, Can Lead To Livelock
A Data Cache Maintenance Operation Which Aborts, Followed By An ISB, Without Any DS
B In-between, Might Lead To Deadlock
Answer Record 52031
Under certain circumstances, a data cache maintenance operation that aborts and is followed by an ISB, without a DSB occurring between these events, might lead to processor deadlock.
This is a third-party errata (ARM, Inc. 775420); this issue will not be fixed.
A Short Loop Including A DM
cacheable
B Instruction Might Cause A Denial Of Service On Another Processor That Is Attempting To Execute A CP15 Broadcast Operation
Answer Record 52032
A short code loop that includes a DM
B instruction might cause a denial of service on another processor that is attempting to execute a CP1
5 broadcast operation.
This is a third-party errata (ARM, Inc. 794072); this issue will not be fixed.
Speculative Instruction Fetches With MMU Disabled Might Not Comply With Architectural Requirements

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