一：本实验设计的是一个8为二进制加法计算器，其功能就是对两个八位的二进制数执行加法运算，并可以异步清零。
二：电路可划分为三部分：半加器、全加器和复位电路。
1、 半加器:
真值表
a
b
so
co
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
电路图
2全加器：由半加器和或门组成
电路图
3复位电路：
复位电路通过en控制，当en为‘1’时，执行加法运算，输出正确的值，当en为‘0’时，输输出及结果为全0.
三：实验波形仿真和VHDL
1、 仿真图：
2、 VHDL代码
1)半加器h_adder：
library ieee;
use ieee.std_logic_1164.all;
entity h_adder is
port (a,b :in std_logic;
2进制转十进制在线计算器    co,so :out std_logic);
end entity h_adder;
architecture fh1 of h_adder is
begin
so <= not(a xor (not b));co <= a and b ;
end architecture fh1;
2)或门or2a：
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port (a,b :in std_logic;
        c: out std_logic);
end entity or2a;
architecture one of or2a is
begin
c <= a or b ;
end architecture one;
3)全加器f_adder：
library ieee;
use ieee.std_logic_1164.all;
entity f_adder is
port (ain,bin,cin:in std_logic;
      cout,sum:out std_logic);
end  entity f_adder;   
architecture fd1 of f_adder is 
component h_adder
port (a,b :in std_logic;
    co,so :out std_logic);
end component;
component or2a
port (a,b :in std_logic;
        c: out std_logic);
end component;
signal d,e,f: std_logic;
begin
u1:h_adder port map(a=>ain,b=>bin,co=>d,so=>e);
u2:h_adder port map(a=>e,b=>cin,co=>f,so=>sum);
u3:  or2a port map(a=>d,b=>f,c=>cout);
end architecture fd1;
4)与门and2a：
library ieee;
use ieee.std_logic_1164.all;
entity and2a is
port (a,b :in std_logic;
        c: out std_logic);
end entity and2a;
architecture one of and2a is
begin
c <= a and b ;
end architecture one;
5)顶层设计文件
library ieee;
use ieee.std_logic_1164.all;
entity zong is
port (a1,a2,a3,a4,a5,a6,a7,a8,b1,b2,b3,b4,b5,b6,b7,b8,en :in std_logic;
        solution1,solution2,solution3,solution4,solution5,solution6,solution7,solution8,solution9 :out std_logic );
end entity zong;
architecture fh1 of zong is
component h_adder
port (a,b :in std_logic;
    co,so :out std_logic);
end component;
component f_adder
port (ain,bin,cin:in std_logic;
      cout,sum:out std_logic);
end component;
component and2a
port (a,b :in std_logic;
        c: out std_logic);
end component;
signal e2,e3,e4,e5,e6,e7,e8,e9,e10,e11,e12,e13,e14,e15,e16,e17,e18,e19,e20,e21,e22,e23,e24 :std_logic;
begin
u1:and2a port map(a=>en,b=>a1,c=>e2);
u2:and2a port map(a=>en,b=>a2,c=>e3);
u3:and2a port map(a=>en,b=>a3,c=>e4);
u4:and2a port map(a=>en,b=>a4,c=>e5);
u5:and2a port map(a=>en,b=>a5,c=>e6);
u6:and2a port map(a=>en,b=>a6,c=>e7);
u7:and2a port map(a=>en,b=>a7,c=>e8);
u8:and2a port map(a=>en,b=>a8,c=>e9);
u9:and2a port map(a=>en,b=>b1,c=>e10);
u10:and2a port map(a=>en,b=>b2,c=>e11);
u11:and2a port map(a=>en,b=>b3,c=>e12);
u12:and2a port map(a=>en,b=>b4,c=>e13);
u13:and2a port map(a=>en,b=>b5,c=>e14);
u14:and2a port map(a=>en,b=>b6,c=>e15);
u15:and2a port map(a=>en,b=>b7,c=>e16);
u16:and2a port map(a=>en,b=>b8,c=>e17);
u17:h_adder port map(a=>e2,b=>e10,co=>e18,so=>solution1);
u18:f_adder port map(ain=>e3,bin=>e11,cin=>e18,cout=>e19,sum=>solution2);
u19:f_adder port map(ain=>e4,bin=>e12,cin=>e19,cout=>e20,sum=>solution3);
u20:f_adder port map(ain=>e5,bin=>e13,cin=>e20,cout=>e21,sum=>solution4);
u21:f_adder port map(ain=>e6,bin=>e14,cin=>e21,cout=>e22,sum=>solution5);
u22:f_adder port map(ain=>e7,bin=>e15,cin=>e22,cout=>e23,sum=>solution6);
u23:f_adder port map(ain=>e8,bin=>e16,cin=>e23,cout=>e24,sum=>solution7);
u24:f_adder port map(ain=>e9,bin=>e17,cin=>e24,cout=>solution9,sum=>solution8);
end architecture fh1;

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