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Features
•Serial Peripheral Interface (SPI) Compatible •Supports SPI Modes 0 (0,0) and 3 (1,1)–Datasheet Describes 0 Operation •
33 MHz Clock Rate
•Byte Mode and 128-byte Page Mode for Program Operations •Sector Architecture:
–Two Sectors with 32K Bytes Each –256 Pages per Sector •Product Identification Mode •Low-voltage Operation –2.7 (V CC = 2.7 to 3.6V)•Sector Write Protectionregister for
•Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection
•Self-timed Program Cycle (75 µs/byte typical)
•Self-timed Sector Erase Cycle (1 second/sector typical)
•Single Cycle Reprogramming (Erase and Program) for Status Register •High Reliability
–Endurance: 10,000 Write Cycles Typical –Data Retention: 20 Years
•
8-lead JEDEC SOIC and 8-lead SAP Packages
Description
The AT25F512A provides 524,288 bits of serial reprogrammable Flash memory orga-nized as 65,536 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25F512A is available in a space-saving 8-lead JEDEC SOIC and
8-lead SAP packages.
The AT25F512A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed.
Block write protection for the entire memory array is enabled by programming the sta-tus register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the Write Protect (WP) pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
Table 1. Pin Configuration
Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect
HOLD
Suspends Serial Input
BDTIC www.BDTIC /ATMEL
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AT25F512A
3345F–FLASH–11/06
Figure 1. Block Diagram
Absolute Maximum Ratings*
Operating Temperature ........................................−40°C to +85°C *NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin
with Respect to Ground ........................................−1.0V to +5.0V Maximum .4.2V DC
5.0 mA
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AT25F512A
3345F–FLASH–11/06
Note:
1.This parameter is characterized and is not 100% tested.
Notes:
1.Preliminary – subject to change
2.V IL and V IH max are reference only and are not tested.
Table 2. Pin Capacitance (1)
Applicable over recommended operating range from T A = 25°C, f = 20 MHz, V CC = +3.6V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions C OUT Output Capacitance (SO)
8pF V OUT = 0V C IN Input Capacitance (CS, SCK, SI, WP , HOLD)6
pF
V IN = 0V
Table 3. DC Characteristics (1)
Applicable over recommended operating range from: T AI = −40 to +85°C, V CC = +2.7 to +3.6V, T AC = 0 to +70°C, V CC = +2.7 to +3.6V (unless otherwise noted)
Symbol Parameter Test Condition
Min Typ
Max Units V CC Supply Voltage 2.7
3.6V I CC1Supply Current V CC = 3.6V at 33 MHz, SO = Open Read 10.015.0mA I CC2Supply Current V CC = 3.6V at 33 MHz, SO = Open Write 25.035.0mA I SB Standby Current V CC = 2.7V, CS = V CC ; SCK, SI, WP , HOLD = 0V or V CC 2.010.0µA I IL Input Leakage V IN = 0V or V CC
−3.0 3.0µA I OL Output Leakage V IN = 0V or V CC , T AI = −40°C to 85°C
−3.0 3.0µA V IL (2)Input Low Voltage −0.6V CC x 0.3V V IH (2)Input High Voltage V CC x 0.7
V CC + 0.5V V OL Output Low Voltage 2.7V ≤ V CC ≤ 3.6V
I OL = 0.15 mA 0.2
V V OH Output High Voltage
I OH = −100 µA
V CC − 0.2
V
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AT25F512A
3345F–FLASH–11/06
Notes:
1.The programming time for n bytes will be equal to n x t BPC .
2.This parameter is ensured by characterization at
3.0V, 25°C only.
3.One write cycle consists of erasing a sector, followed by programming the same sector.
Table 4. AC Characteristics (Preliminary - Subject to Change)
Applicable over recommended operating range from T AI = −40 to +85°C, V CC = +2.7 to +3.6V C L = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter
Min Typ
Max Units f SCK SCK Clock Frequency 0
33MHz t RI Input Rise Time 20ns t FI Input Fall Time 20
ns t WH SCK High Time 9ns t WL SCK Low Time 9ns t CS CS High Time 25ns t CSS CS Setup Time 25ns t CSH CS Hold Time 10ns t SU Data In Setup Time 5ns t H Data In Hold Time 5ns t HD Hold Setup Time 15ns t CD Hold Time 15
ns t V Output Valid 9
ns t HO Output Hold Time 0
ns t LZ Hold to Output Low Z 200ns t HZ Hold to Output High Z 200ns t DIS Output Disable Time 100ns t EC Erase Cycle Time per Sector 1.1s t SR Status Register Write Cycle Time 60ms t BPC
Byte Program Cycle Time (1)
75100
µs Endurance (2)10K
Write Cycles (3)
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AT25F512A
3345F–FLASH–11/06
Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the SCK pin is always an input, the AT25F512A always operates as a slave.
TRANSMITTER/RECEIVER:The AT25F512A has separate pins designated for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25F512A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication.CHIP SELECT: The AT25F512A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F512A.When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The AT25F512A has a write lockout feature that can be activated by asserting the
WP pin. When the lockout feature is activated, locked-out sectors will be read only. The write protect pin will allow normal read/write operations when held high.When the WP is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register.If the internal status register write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25F512A in a system with the WP pin tied to ground and still be able to write to the sta-tus register. All WP pin functions are enabled when the WPEN bit is set to “1”.
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