AS8202B
TTP-C2NF Communication Controller
1 General Description
The AS8202B communication controller is an integrated device supporting serial communication accordi
ng to the TTP specification version 1.1. It performs all communication tasks such as reception and transmission of messages in a TTP cluster without interaction of the host CPU. TTP provides mechanisms that allow the deployment in high-dependability distributed real-time systems. It provides the following services:
⏹ Predictable transmission of messages with minimal jitter
⏹ Fault-tolerant distributed clock synchronization
⏹ Consistent membership service with small delay
⏹ Masking of single faults
2 Key Features
⏹ Dual-channel controller for redundant data transfers
⏹ Dedicated controller supporting TTP (time-triggered protocol
class C standardized in SAE 6003)
⏹ Suited for dependable distributed real-time systems with
guaranteed response time
⏹ Asynchronous data rate up to 4 Mbit/s (MFM/Manchester)
⏹ Synchronous data rate 20 to 25 Mbit/s
⏹ Bus interface (speed, encoding) for each channel selectable
independently
⏹ 40 MHz oscillator clock support
⏹ 16 MHz bus guardian clock with support for 16 MHz crystal or
16 MHz oscillator
⏹ Single power supply 3.3V, 0.35µm CMOS process
⏹ Full automotive temperature range (-40ºC to 125ºC)
⏹ 16k x 16 SRAM for message, status, control area
(communication network interface) and for scheduling
information (MEDL)
⏹ 4k x 16 (plus parity) instruction code RAM for protocol execution
code
⏹ Datasheet conforms to protocol revision 2.05
⏹ 16k x 16 instruction code ROM containing startup execution
code and deprecated protocol code revision 1.00
⏹ 16-bit non-multiplexed asynchronous host CPU interface
⏹ 16-bit RISC architecture
⏹ Software tools, design support, development boards available
h
⏹ Certification support package according to RTCA/DO-254 DAL
A available – h
⏹ RoHS conform
3 Applications
The device is ideal for application fields such as, aerospace according to DO-254 level A (e.g. flight control, power distribution, engine control), industrial systems, and railway systems.
Contents
1  General Description (1)
2  Key Features (1)
3  Applications (1)
4  Pin Assignments (3)
4.1  Pin Descriptions (3)
5  Absolute Maximum Ratings (6)
6  Electrical Characteristics (7)
7  Detailed Description (9)
7.1  Host CPU Interface (9)
7.1.1  Synchronous READYB Generation (12)
7.2  Reset and Oscillator (13)
7.2.1  External Reset Signal (13)
7.2.2  Integrated Power-On Reset (13)
7.2.3  Oscillator Circuitry (13)
7.2.4  Built-in Characteristics (14)
7.3  TTP Bus Interface (14)
7.4  TTP Asynchronous Bus Interface (15)
7.5  TTP Synchronous Bus Interface (15)
7.6  Test Interface (16)
7.7  LED Signals (16)
8  Package Drawings and Markings (17)
9  Ordering Information (19)
4 Pin Assignments
4.1 Pin Descriptions
connect下载Table 1.  Pin Descriptions
Pin Name Pin Number Dir Description
VDD4, 12, 29, 49, 59, 74
Power pin Positive Power Supply
VSS13, 30, 41, 50, 60,
75, 80
Negative Power Supply
VDDBG70Positive Power Supply for Bus Guardian (connect to VDD) VSSBG73Negative Power Supply for Bus Guardian (connect to VSS)
RAM_CLK_TESTSE
21TTL Input with internal weak pull-down
RAM_CLK when STEST=0 and USE_RAM_CLK=1, else Test Input, connect to VSS if not used
STEST 22Test Input, connect to VSS
FTEST 24Test Input, connect to VSS
FIDIS 25Test Input, connect to VSS
TTEST 61TTL Input with internal weak pull-up
Test Input, connect to VDD
USE_RAM_CLK
34TTL Input with internal weak pull-down
RAM_CLK Pin Enable, connect to VSS if not used
XIN02Analog CMOS pin
Main Clock: 40MHz external clock input CTEST 3Test input, to be unconnected
OSCMODE 23TTL Input with internal weak pull-down
Connect to VDD 1
XIN172
Analog CMOS pin
Bus Guardian Clock: Analog CMOS Oscillator Input, use as input when providing external clock
XOUT171Bus Guardian Clock: Analog CMOS Oscillator Output, leave open when providing external clock
RESETB 26TTL Input with internal weak pull-up Main Reset Input, active low
TxD05TTL output with internal weak pull-up at tristate TTP Bus Channel 0: Transmit Data
CTS06TTL output with internal weak pull-down at tristate TTP Bus Channel 0: Transmit Enable
RxD011TTL Input with internal weak pull-up
TTP Bus Channel 0: Receive Data
TxCLK07TTL Input with internal weak pull-down TTP Bus Channel 0: Transmit Clock (MII mode)
RxER08TTL Input with internal weak pull-up TTP Bus Channel 0: Receive Error (MII mode)
RxCLK09TTL Input with internal weak pull-down TTP Bus Channel 0: Receive Clock (MII mode)
RxDV010TTL Input with internal weak pull-up TTP Bus Channel 0: Receive Data Valid (MII mode)
TxD114TTL output with internal weak pull-up at tristate TTP Bus Channel 1: Transmit Data
CTS115TTL output with internal weak pull-down at tristate TTP Bus Channel 1: Transmit Enable
RxD120TTL Input with internal weak pull-up
TTP Bus Channel 1: Receive Data
TxCLK116TTL Input with internal weak pull-down TTP Bus Channel 1: Transmit Clock (MII mode)
RXER117TTL Input with internal weak pull-up TTP Bus Channel 1: Receive Error (MII mode)
RXCLK118TTL Input with internal weak pull-down TTP Bus Channel 1: Receive Clock (MII mode)
RxDV1
19
TTL Input with internal weak pull-up
TTP Bus Channel 1: Receive Data Valid (MII mode)
Table 1.  Pin Descriptions
Pin Name  Pin Number
Dir
Description
A[11:0]48-42, 39-35TTL Input
Host Interface (CNI) Address Bus
2
D[15:0]69-62, 58-51
TTL input/output with tristate Host Interface (CNI) Data Bus, tristate
CEB 76TTL Input with internal weak pull-up
Host Interface (CNI) chip enable, active low
OEB 77Host interface (CNI) output enable, active low
WEB 78Host interface (CNI) write enable, active low
READYB 79TTL output with internal weak pull-up at tristate
Host interface (CNI) transfer finish signal, active low, open
drain
3
INTB 28Host interface (CNI) time signal (interrupt), active low, open drain LED[2:0]33-31TTL output with internal weak pull-down at tristate
Configurable generic output port
NC
1, 27, 40
Not connected, leave open
1.This pin selects a clock multiplier of 1. This is the only supported operation mode.
2.The device is addressed at 16-bit data word boundaries. If the device is connected to a CPU with a byte-granular address bus, remem-ber that A[11:0] of the AS8202B device has to be connected to A[12:1] of the CPU (considering a little endian CPU address bus)
3.At de-assertion READYB is driven to the inactive value (high) for a configurable time.
Table 1.  Pin Descriptions
Pin Name  Pin Number Dir Description

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