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Virtex Pin Definitions
Virtex™ 2.5 V
Field Programmable Gate Arrays
DS003-4 (v2.8) July 19, 2002Production Product Specification
Table  1:  Special Purpose Pins
Pin Name
Dedicated
Pin
Direction
Description
GCK0, GCK1, GCK2, GCK3Y es Input Clock input pins that connect to Global Clock Buffers. These pins become user inputs when not needed for clocks.
M0, M1, M2Y es Input
Mode pins are used to specify the configuration mode.
CCLK
Y es
Input or Output The configuration Clock I/O pin: it is an input for SelectMAP and
slave-serial modes, and output in master-serial mode. After configuration, it is input only, logic level =
Don’t Care.
PROGRAM Y es Input Initiates a configuration sequence when asserted Low.
DONE Y es Bidirectional Indicates that configuration loading is complete, and that the start-up sequence is in progress. The output can be open drain.
INIT No Bidirectional (Open-drain)When Low, indicates that the configuration memory is being cleared. The pin becomes a user I/O after configuration.
BUSY/DOUT
No
Output
In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration unless the SelectMAP port is retained.
In bit-serial modes, DOUT provides header information to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration.
D0/DIN,D1, D2,D3, D4,D5, D6,D7No
Input or Output
In SelectMAP mode, D0 - D7 are configuration data pins. These pins become user I/Os after configuration unless the SelectMAP port is retained.
In bit-serial modes, DIN is the single data input. This pin becomes a user I/O after configuration.
WRITE No Input In SelectMAP mode, the active-low Write Enable signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained.CS No Input In SelectMAP mode, the active-low Chip Select signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained.TDI, TDO,TMS, TCK Y es Mixed Boundary-scan T est-Access-Port pins, as defined in IEEE 1149.1.DXN, DXP Y es N/A Temperature-sensing diode pins. (Anode: DXP , cathode: DXN)V CCINT Y es Input Power-supply pins for the internal core logic.
V CCO Y es Input Power-supply pins for the output drivers (subject to banking rules)V REF No Input Input threshold voltage pins. Become user I/Os when an external threshold voltage is not needed (subject to banking rules).GND
Y es
Input
Ground
Virtex Pinout Information
Pinout Tables
See www.xilinx for updates or additional pinout information. For convenience, Table2, T able3 and Table4 list the locations of special-purpose and power-supply pins. Pins not listed are either user I/Os or not connected, depending on the device/package combination. See the Pinout Diagrams starting on page17 for any pins not listed for a particular part/package combination.
Table  2:  Virtex Pinout Tables (Chip-Scale and QFP Packages)
Pin Name Device CS144TQ144PQ/HQ240
GCK0All K79092
connect下载
GCK1All M79389
GCK2All A719210
GCK3All A616213
M0All M111060
M1All L211258
M2All N210862
CCLK All B1338179
PROGRAM All L1272122
DONE All M1274120
INIT All L1371123
BUSY/DOUT All C1139178
D0/DIN All C1240177
D1All E1045167
D2All E1247163
D3All F1151156
D4All H1259145
D5All J1363138
D6All J1165134
D7All K1070124
WRITE All C1032185
CS All D1033184
TDI All A1134183
TDO All A1236181
TMS All B11432
TCK All C32239
V CCINT All A9, B6, C5, G3,
G12, M5, M9, N610, 15, 25, 57, 84, 94,
99, 126
16, 32, 43, 77, 88, 104,
137, 148, 164, 198,
214, 225
V CCO All Banks 0 and 1:
A2, A13, D7
Banks 2 and 3:
B12, G11, M13
Banks 4 and 5:
N1, N7, N13
Banks 6 and 7:
B2, G2, M2No I/O Banks in this
package:
1, 17, 37, 55, 73, 92,
109, 128
No I/O Banks in this
package:
15, 30, 44, 61, 76, 90,
105, 121, 136, 150, 165,
180, 197, 212, 226, 240
V REF, Bank 0
(V REF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.)
Within each bank, if input reference voltage is not required, all
V REF pins are general I/O.XCV50C4, D65, 13218, 232 + B4... + 7... + 229 XCV200/300N/A + 236 XCV400N/A + 215 XCV600N/A + 230 XCV800N/A + 222
V REF, Bank 1
(V REF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.)
Within each bank, if input reference voltage is not required, all
V REF pins are general I/O.
XCV50A10, B822, 30191, 205 + D9... + 28... + 194 XCV200/300N/A + 187 XCV400N/A + 208 XCV600N/A + 193 XCV800N/A + 201
V REF, Bank 2
(V REF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.)
Within each bank, if input reference voltage is not required, all
V REF pins are general I/O.
XCV50D11, F1042, 50157, 171 + + 44... + 168 XCV200/300N/A + 175 XCV400N/A + 154 XCV600N/A + 169 XCV800N/A + 161
Table  2:  Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)
Pin Name Device CS144TQ144PQ/HQ240
V REF, Bank 3
(V REF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.)
Within each bank, if input reference voltage is not required, all
V REF pins are general I/O.
XCV50H11, K1260, 68130, 144 + + 66... + 133 XCV200/300N/A + 126 XCV400N/A + 147 XCV600N/A + 132 XCV800N/A + 140
V REF, Bank 4
(V REF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.)
Within each bank, if input reference voltage is not required, all
V REF pins are general I/O.
XCV50L8, L1079, 8797, 111 + + 81... + 108 XCV200/300N/A + 115 XCV400N/A + 94 XCV600N/A + 109 XCV800N/A + 101
V REF, Bank 5
(V REF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.)
Within each bank, if input reference voltage is not required, all
V REF pins are general I/O.
XCV50L4, L696, 10470, 84 + N4... + + 73 XCV200/300N/A + 66 XCV400N/A + 87 XCV600N/A + 72 XCV800N/A + 80
Table  2:  Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)
Pin Name Device CS144TQ144PQ/HQ240
V REF, Bank 6
(V REF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.)
Within each bank, if input reference voltage is not required, all
V REF pins are general I/O.
XCV50H2, K1116, 12336, 50 + J3... + + 47 XCV200/300N/A + 54 XCV400N/A + 33 XCV600N/A + 48 XCV800N/A + 40
V REF, Bank 7
(V REF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.)
Within each bank, if input reference voltage is not required, all
V REF pins are general I/O.
XCV50D4, E1133, 1409, 23 + D2... + + 12 XCV200/300N/A + 5 XCV400N/A + 26 XCV600N/A + 11 XCV800N/A + 19
GND All A1, B9, B11, C7,
D5, E4, E11, F1,
G10, J1, J12, L3,
L5, L7, L9, N12
9, 18, 26, 35, 46, 54, 64,
75, 83, 91, 100, 111, 120,
129, 136, 144,
1, 8, 14, 22, 29, 37, 45, 51,
59, 69, 75, 83, 91, 98, 106,
112, 119, 129, 135, 143,
151, 158, 166, 172, 182,
190, 196, 204, 211, 219,
227, 233
Table  2:  Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)
Pin Name Device CS144TQ144PQ/HQ240

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