DFT_Compiler使用说明
摘要：本文档介绍了DFT_Compiler的基本使用，分基本流程框图和基本操作内容两部分，二者是相互对应的，流程框图是对整个过程的总体说明，操作内容是是对过程的具体实现以及对为什么要进行对应过程的基本解释。
一、基本流程框图
二、基本操作内容
I. Preparing to Run DFT Compiler
Before running DFT Compiler, you need to set up your interface, prepare your design environment, and read in your design. This section covers the following topics:
• Invoking the Synthesis Tool
• Setting Up Your Design Environment
• Reading In Your Design
• Setting the Scan Style
• Configuring the Test Cycle Timing
• Defining the DFT Signals
1. Invoking the Synthesis Tool
You can use DFT Compiler from within any of the following synthesis tools:
* Design Compiler
* Design Vision
* DC Explorer
2. Setting Up Your Design Environment
To set up your design environment, you need to define the paths for the logic libraries and designs you are using, and define any special reporting parameters.
# configure logic libraries
set search_path /lib_path ##注意对库路径的正确设置
set target_library {library.db}
set link_library {* library.db} ##注意*号不能丢，且其后有空格3. Reading In Your Design
To read in your design, specify the appropriate file read commands depending on the file format: read_ddc, read_verilog, read_vhdl. The following example reads in a list of Verilog files:
read_verilog {/top_path/top.v /block_path/block.v} ##注意对设计路径的正确设置Use the current_design and link commands to link the top level of the current design: current_design top
link
If DFT Compiler is unable to resolve any references, you must provide the missing designs before proceeding. After linking, use the read_sdc command (or the source command) to apply the design constraints:
read_sdc top_constraints.sdc
Note:
If you read in the top-level design in the Synopsys logic database (.ddc) format, the design constraints might already be applied.
4. Setting the Scan Style
DFT Compiler uses the selected scan style to perform scan synthesis. A scan style dictates the appropriate scan cells to insert during optimization. This scan style is used on all modules of your design.
set_scan_configuration -style multiplexed_flip_flop
The default style is multiplexed flip-flop. To specify another scan style, use the –style option of the set_scan_configuration command. For example,
set_scan_configuration -style clocked_scan
5. Configuring the Test Cycle Timing（*）
Set the test timing variables to the values required by your ASIC vendor. If you are using TetraMAX ATPG to generate test patterns, and your vendor does not have specific requirements, the default settings produce the best results:
set_app_var test_default_delay 0
set_app_var test_default_bidir_delay 0
set_app_var test_default_strobe 40
set_app_var test_default_period 100
These are the default settings; you do not need to add them to your script.
6. Defining the DFT Signals
Most DFT Compiler commands include the concept of a view, specified with the –view option. The valid view values are:
* -view existing_dft
The existing DFT view is descriptive and describes an existing signal network. An example is an existing functional clock signal that is also used as a scan clock in test mode.
* -view spec
The specification view is prescriptive and describes action that must be taken during DFT insertion. It indicates that the signal network does not yet exist, and the insert_dft command must add it. An example is a scan-enable signal network that must be routed to all scannable flip-flops during DFT insertion.
A view is typically specified in scan specification commands, such as set_dft_signal. When performing
scan synthesis, you use a combination of the two views. When you define existing signals that are used in test mode, you use the existing DFT view. When you define the DFT structure you want inserted, you use the specification view. Define any clocks and asynchronous set and reset signals in the existing DFT view: set_dft_signal -view existing_dft -type ScanClock ...
set_dft_signal -view existing_dft -type Reset ...
If you have a dedicated scan-enable port, define it in the specification view:
set_dft_signal -view spec -type ScanEnable -port scan_enable_port -active_state 1
If no scan-enable port is identified, DFT Compiler creates a new scan-enable port.
If you are using existing ports as scan-in and scan-out ports, define them in the specification view (even if they have existing functional logic connections):
set_dft_signal -view spec -type ScanDataIn -port DAT_IN[7]
...
set_dft_signal -view spec -type ScanDataIn -port DAT_IN[0]
set_dft_signal -view spec -type ScanDataOut -port DAT_OUT[7]
...
set_dft_signal -view spec -type ScanDataOut -port DAT_OUT[0]
Otherwise, DFT Compiler creates new scan-in and scan-out ports as needed.
II. Performing Scan Synthesis
The scan synthesis process tests and prepares your RTL design for test-ready compilation, synthesizes it, tests it again, performs scan insertion, and analyzes your post-DFT design.
This section covers the following processes:
• Performing RTL Test Design Rule Checking
• Performing One-Pass Scan Synthesis
• Performing Scan Insertion
• Performing Post-DFT Optimization
Note:
The first two steps pertain only to RTL designs. If your design is already mapped to logic gates, start with the Performing Pre-DFT Test DRC step.
1. Performing RTL Test Design Rule Checkingdefine的基本用法
RTL test DRC provides early warnings of test-related issues, based on the scan style specified by the set_scan_configuration command. By correcting these problems before the compile phase, you can reduce time-consuming iterations that occur later in the design process. This section provides an overview of the RTL test design rule checking process. To perform RTL test design rule checking:
(1).Configure your design for scan testing by generating a test protocol:
create_test_protocol
(2).Run RTL test design rule checking by using the dft_drc command:
dft_drc
(3).Check for violations, then do one of the following:
* If violations are reported, change the RTL code and repeat steps (1) and (2).
* If no violations are reported, proceed to one-pass scan synthesis.
2. Performing One-Pass Scan Synthesis
After fixing all violations during the RTL test DRC process, you are ready to perform one-pass scan synthesis, which performs test-ready compilation. To do this, specify the compile -scan command, as shown in the following example:
compile -scan
When using the DC Ultra tool (such as with topographical mode), use the following command:
compile_ultra -scan
The -scan option performs a test-ready compile, which maps directly to scan cells. This helps eliminate logically untestable circuitry and is an important part of the Synopsys test methodology. The resulting netlist with unstitched scan cells is called an unrouted scan design.
3. Performing Scan Insertion
The scan insertion process consists of four primary phases:
•Configuring Scan Insertion
•Previewing Scan Insertion
•Performing Pre-DFT Test DRC
•Inserting the DFT Logic
3.1 Configuring Scan Insertion
To configure scan insertion, you can specify test ports, define test modes, and identify and mark any cells that you do not want to have scanned. You can set many of these configuration parameters by using commands such as set_scan_configuration, set_dft_signal, or set_scan_element.
The following example shows some typical DFT configuration commands:
set_scan_configuration -chain_count 4
set_dft_signal -view spec -type ScanDataIn -port TEST_SI
set_dft_signal -view spec -type ScanDataOut -port TEST_SO
set_dft_signal -view spec -type ScanEnable -port TEST_SE
3.2 Previewing Scan Insertion
Before performing scan insertion, you can preview your scan design by running the preview_dft command. This command generates a scan chain design that satisfies scan specifications on your current design and displays the scan chain design. This allows you to preview your scan chain design without synthesizing it and change your specifications as necessary. The following example shows how to specify the preview_dft command:
preview_dft
3.3 Performing Pre-DFT Test DRC
Pre-DFT test design rule checking (DRC) process analyzes your unrouted scan design, based on a set of constraints applicable to your selected scan style, then outputs a set of violations. Based on the violations, you make changes to your design to prepare it for DFT insertion.
To perform pre-DFT test design rule checking,
(1). Create the test protocol.
You can use the test protocol definition you previously used for RTL test DRC, but you must still regenerate it.
create_test_protocol
(2). Run pre-DFT test DRC.
dft_drc
(3). Check for violations, then do one of the following:
* If violations are reported, make changes to the design or test protocol and repeat steps (1) and( 2).
* If no violations are reported, proceed to scan insertion.
3.4 Inserting the DFT Logic
After configuring and previewing your design, assemble the scan chains by using the insert_dft command:
insert_dft
4. Performing Post-DFT Optimization
Post-DFT optimization is gate-level optimization performed after inserting and mapping the new DFT structures. It performs optimizations such as selecting scan-out signal connections (Q or QN) to minimize constraint violations. This reduces the
scan-related overhead on timing performance and area, and it eliminates synthesis design rule errors. The insert_dft command creates scan chains that are functional under zero-delay assumptions using the scan clock waveforms described by the set_dft_signal command. However, post-DFT optimization uses the clock waveforms described by the create_clock command; it does not use the scan clock timing values described by the set_dft_signal command. The post-DFT optimization flow depends on the Design Compiler mode.
(1) Post-DFT Optimization in Design Compiler Wire Load Mode
In Design Compiler wire load mode, the insert_dft command automatically performs basic gate-level post-DFT optimization by default. If needed, you can disable it with the following command:
set_dft_insertion_configuration -synthesis_optimization none
In this case, you can still manually perform a post-DFT incremental compile if you disable automatic post-DFT synthesis optimization:
# for a DC Expert compile
insert_dft
compile -scan –incremental
# for a DC Ultra compile
insert_dft
compile_ultra -scan -incremental
(2) Post-DFT Optimization in Design Compiler Topographical Mode
In Design Compiler topographical mode, the insert_dft command maps new logic, but does not perform post-DFT optimization. In this mode, you perform post-DFT optimization by manually running
an incremental post-DFT topographical compile after the insert_dft command completes. For example,
insert_dft
compile_ultra -scan –incremental
Design Compiler synthesis optimizes the newly inserted DFT logic, and it optimizes the design to accommodate the additional area and timing overhead of the DFT logic.
III. Analyzing Y our Post-DFT Design
After you perform DFT insertion, you should perform design rule checking again to ensure that no new violations have been introduced into your design:
dft_drc
This is called post-DFT DRC. DFT Compiler checks for and describes potential problems with the testability of your design. These checks are more comprehensive than those in pre-DFT DRC, and they check for the correct operation of the scan chain. After you correct all the reported violations, you can proceed with the next step.
IV. Reporting
All DFT specification commands have corresponding reporting commands. To report what exists in the design, use the -view existing_dft option of the reporting command. To report what you have specified for insertion, use the -view spec option, which is also the default.

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