12/15/06
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AFL120XXD SERIES
The AFL Series of DC/DC converters feature high power density with no derating over the full military temperature range. This series is offered as part of a complete family of converters providing single and dual output voltages and operating from nominal +28V or +270V inputs with output power ranging
from 80W to 120W. For applications requiring higher output power, individual converters can be operated in parallel. The internal current sharing circuits assure equal current distribution among the paralleled converters. This series incorporates International Rectifier’s proprietary magnetic pulse feedback technology providing optimum dynamic line and load regulation response. This feedback system samples the output voltage at the pulse width modulator fixed clock frequency, nominally 550KHz. Multiple converters can be synchronized to a system clock in the 500KHz to 700KHz range or to the synchronization output of one converter.  Undervoltage lockout, primary and secondary referenced inhibit, soft-start and load fault protection are provided on all models.
Description
n 80V To 160V Input Range
n ±5V, ±12V, and ±15V Outputs Available n High Power Density - up to 70W/in 3n Up To 100W Output Power
n Parallel Operation with Power Sharing
n Low Profile (0.380") Seam Welded Package n Ceramic Feedthru Copper Core Pins n High Efficiency - to 87%
n Full Military T emperature Range
n Continuous Short Circuit and Overload      Protection
n Output Voltage Trim
n Primary and Secondary Referenced      Inhibit  Functions
n Line Rejection > 50dB - DC to 50KHz n External Synchronization Port n Fault Tolerant Design
n Single Output Versions Available
n Standard Microcircuit Drawings Available
Features
AFL
120V Input, Dual Output
Manufactured in a facility fully qualified to MIL-PRF-38534, these converters are fabricated utilizing DS
CC qualified processes. For available screening options,refer to device screening table in the data sheet.Variations in electrical, mechanical and screening can be accommodated.  Contact IR Santa Clara for special requirements.
HYBRID-HIGH RELIABILITY
DC/DC CONVERTER
These converters are hermetically packaged in two enclosure variations, utilizing copper core pins to minimize resistive DC losses.  Three lead styles are available, each fabricated with International Rectifier’s rugged ceramic lead-to-package seal assuring long term hermeticity in the most harsh environments.PD - 94463C
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AFL120XXD Series
Specifications
Static Characteristics  -55°C < T CASE  < +125°C,  80V< V IN  < 160V  unless otherwise specified.
For Notes to Specifications, refer to page 4
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AFL120XXD Series
Static Characteristics  (Continued)
For Notes to Specifications, refer to page 4
Parameter
Group A Subgroups
Test Conditions
Min  Nom  Max  Unit OUTPUT RIPPLE VOLTAGE  AFL12005D  AFL12012D  AFL12015D
1, 2, 3
1, 2, 3
1, 2, 3 V IN  = 80, 120, 160 Volts, 100% Load,
BW = 10MHz
60 80 80  mV pp  INPUT CURRENT
No Load
Inhibit 1  Inhibit 2  1 2, 3 1, 2, 3 1, 2, 3 V IN  = 120 Volts I OUT  = 0  Pin 4 Shorted to Pin 2 Pin 12 Shorted to Pin 8
20 25 3.0 5.0  mA  INPUT RIPPLE CURRENT  AFL12005D  AFL12012D  AFL12015D  1, 2, 3
1, 2, 3 1, 2, 3 V IN  = 120 Volts, 100% Load
60 70 80  mA pp  CURRENT LIMIT POINT
Expressed as a Percentage
of Full Rated Load
1 2 3 V OUT  = 90% V NOM  , Current split
equally on positive and negative outputs.  Note 5
115 105 125
125 115 140
%  LOAD FAULT POWER DISSIPATION  Overload or Short Circuit
1, 2, 3
V IN  = 120 Volts
32
W EFFICIENCY
AFL12005D  AFL12012D  AFL12015D
1, 2, 3 1, 2, 3 1, 2, 3 V IN  = 120 Volts, 100% Load  78 82 83  82 85 87
%  ENABLE INPUTS (Inhibit Function)
Converter Off
Sink Current
Converter On  Sink Current  1, 2, 3  1, 2, 3  Logical Low on Pin 4 or Pin 12 Note 1 Logical High on Pin 4 and Pin 12 - Note 9
Note 1  -0.5  2.0
0.8 100 50 100  V µA V µA SWITCHING FREQUENCY
1, 2, 3
500 550 600 KHz SYNCHRONIZATION INPUT
Frequency Range
Pulse Amplitude, Hi
Pulse Amplitude, Lo  Pulse Rise Time  Pulse Duty Cycle  1, 2, 3 1, 2, 3 1, 2, 3
Note 1 Note 1
500 2.0 -0.5  20
700 10 0.8 100 80
KHz V V ns %
ISOLATION    1 Input to Output or Any Pin to Case (except Pin 3).  Test @ 500VDC 100  M Ω DEVICE WEIGHT  Slight Variations with Case Style
85
g
MTBF
MIL-HDBK-217F, AIF @ T C  = 40°C
300  KHrs
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AFL120XXD Series
Dynamic Characteristics  -55°C < T CASE  < +125°C,  V IN =120V  unless otherwise specified.
Notes to Specifications:
1.Parameters not 100% tested but are guaranteed to the limits specified in the table.
2.
Recovery time is measured from the initiation of the transient to where V out  has returned to within ±1.0% of V out  at 50% load.
3.Line transient transition time ≥ 100µs.
profile中文
4.Turn-on delay is measured with an input voltage rise time of between 100V and 500V per millisecond.
5.Current limit point is that condition of excess load causing output voltage to drop to 90% of nominal.
6.Parameter verified as part of another test.
7.All electrical tests are performed with the remote sense leads connected to the output leads at the load.8.Load transient transition time ≥ 10µs.
9.Enable inputs internally pulled high.  Nominal open circuit voltage ≈ 4.0VDC.10.Load current split equally between +V out  and -V out .
11.Output load must be distributed so that a minimum of 20% of the total output power is being provided by one of
the outputs.
12.Cross regulation measured with load on tested output at 20% of maximum load while changing the load on
other output from 20% to 80%.
Parameter
Group A Subgroups
Test Conditions
Min  Nom  Max  Unit LOAD TRANSIENT RESPONSE  AFL12005D Amplitude  Either Output Recovery  Amplitude  Recovery
AFL12012D Amplitude  Either Output Recovery  Amplitude  Recovery
AFL12015D Amplitude  Either Output Recovery  Amplitude  Recovery
4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6  4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6  4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6
Note 2, 8
Load Step  50% ⇔ 100%
Load Step  10% ⇔ 50%
10% ⇒ 50%  50% ⇒ 10% Load Step  50% ⇔ 100%
Load Step  10% ⇔ 50%  10% ⇒ 50%  50% ⇒ 10% Load Step  50% ⇔ 100%
Load Step  10% ⇔ 50%
10%
⇒ 50%  50% ⇒ 10%
-450  -450  -750  -750  -750  -750
450 200 450 200 400 750 200 750 200 400 750 200 750 200 400
mV µs mV µs µs mV µs mV µs µs mV µs mV µs µs
LINE TRANSIENT RESPONSE  Amplitude
Recovery
Note 1, 2, 3
V IN  Step = 80 ⇔ 160 Volts  -500
500 500  mV µs TURN-ON CHARACTERISTICS    Overshoot
Delay
4, 5, 6 4, 5, 6 Note 4
Enable 1, 2 on.  (Pins 4, 12 high or open)
50  75  250 120  mV ms LOAD FAULT RECOVERY  Same as Turn On Characteristics.
LINE REJECTION
MIL-STD-461D, CS101, 30Hz to 50KHz Note 1 50 60  dB
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Figure II.  Enable Input Equivalent Circuit
Pin 4 or Pin 12
Pin 2 or Pin 8
The switched voltage impressed on the secondary output transformer windings is rectified and filtered to provide the positive and negative converter output voltages.  An error amplifier on the secondary side compares the positive output voltage to a precision reference and generates an error signal proportional to the difference.  This error signal is magnetically coupled through the feedback transformer into the control section of the converter varying the pulse width of the square wave signal driving the MOSFETs, narrowing the pulse width if the output voltage is too high and widening it if it is too low.  These pulse width variations provide the necessary corrections to regulate the magnitude of output voltage within its’ specified limits.
Because the primary portion of the circuit is coupled to the secondary side with magnetic elements, full isolation from input to output is maintained.
ancilliary features, basic operation of the  AFL120XXDseries can be initiated by simply applying an inp
ut voltage to pins 1and 2 and connecting the appropriate loads between pins 7,8, and 9. Of course, operation of any converter with high power density should not be attempted before secure attachment to an appropriate heat dissipator. (See Thermal Considerations, page 7)
Inhibiting Converter Output (Enable)
As an alternative to application and removal of the DC voltage to the input, the user can control the converter output by providing TTL compatible, positive logic signals to either of two enable pins (pin 4 or 12).  The distinction between these two signal ports is that enable 1 (pin 4) is referenced to the input return (pin 2) while enable 2 (pin 12) is referenced to the output return (pin 8).  Thus, the user has access to an inhibit function on either side of the isolation barrier.  Each port is internally pulled “high” so that when not used, an open connection on both enable pins permits normal converter operation.  When their use is desired, a logical “low” on either port will shut the converter down.
The AFL series of converters employ a forward switched mode converter topology. (refer to Figure I.)  Operation of the device is initiated when a DC voltage whose magnitude is within the specified input limits is applied between pins 1and 2.  If pins 4 and 12 are enabled (at a logical 1 or open)the primary bias supply will begin generating a regulated housekeeping voltage bringing the circuitry on the primar
y side of the converter to life.  Two power MOSFETs used to chop the DC input voltage into a high frequency square wave, apply this chopped voltage to the power transformer.As this switching is initiated, a voltage is impressed on a second winding of the power transformer which is then rectified and applied to the primary bias supply.  When this occurs, the input voltage is excluded from the bias voltage generator and the primary bias voltage becomes internally generated.
CASE
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AFL120XXD Series
Figure III.  Preferred Connection for Parallel Operation
Synchronization of Multiple Converters
Parallel Operation-Current and Stress Sharing
Internally, these ports differ slightly in their function.  In use,a low on Enable 1 completely shuts down all circuits in the converter, while a low on Enable 2 shuts down the secondary side while altering the controller duty cycle to near zero.Externally, the use of either port is transparent to the user save for minor differences in idle current. (See specification table).
When operating multiple converters, system requirements often dictate operation of the converters at a common frequency. To accommodate this requirement, the AFL series converters provide both a synchronization input and output.
The sync input port permits synchronization of an AFL converter to any compatible external frequency source operating between 500KHz and 700KHz. This input signal should  be referenced to the input return and have a 10% to 90% duty cycle.  Compatibility requires transition times less than 100ns, maximum low level of +0.8V and a minimum high level of +2.0V. The sync output of another converter
which has been designated as the master oscillator provides a convenient frequency source for this mode of operation.When external synchronization is not indicted, the  sync in pin should be left unconnected thereby permitting the converter to operate at its’ own internally set frequency.The sync o
utput signal is a continuous pulse train set at 550 ± 50KHz, with a duty cycle of 15 ± 5.0%. This signal is referenced to the input return and has been tailored to be compatible with the AFL sync input port. Transition times are less than 100ns and the low level output impedance is less than 50Ω. This signal is active when the DC input voltage is within the specified operating range and the converter is not inhibited.  This synch output has adequate drive reserve to synchronize at least five additional converters.  A typical synchronization connection option is illustrated in Figure III.
(Other Converters)
Figure III. illustrates the preferred connection scheme for operation of a set of AFL converters with outputs operating in parallel. Use of this connection permits equal current sharing among the members of a set whose load current exceeds the capacity of an individual AFL. An important
feature of the AFL series operating in the parallel mode is that in addition to sharing the current, the stress induced by temperature will also be shared.  Thus if one member of a paralleled set is operating at a higher case temperature, the current it provides to the load will be reduced as compensation for the temperature induced stress on that device.

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